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Message-ID: <trinity-2ee224b5-cbac-415e-9f8c-305e802b5369-1522232002354@3c-app-gmx-bs61>
Date: Wed, 28 Mar 2018 12:13:22 +0200
From: "Lino Sanfilippo" <LinoSanfilippo@....de>
To: "Benjamin Herrenschmidt" <benh@...nel.crashing.org>
Cc: "Will Deacon" <will.deacon@....com>,
"Linus Torvalds" <torvalds@...ux-foundation.org>,
"Alexander Duyck" <alexander.duyck@...il.com>,
"Sinan Kaya" <okaya@...eaurora.org>,
"Arnd Bergmann" <arnd@...db.de>, "Jason Gunthorpe" <jgg@...pe.ca>,
"David Laight" <David.Laight@...lab.com>,
Oliver <oohall@...il.com>,
"open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)"
<linuxppc-dev@...ts.ozlabs.org>,
"linux-rdma@...r.kernel.org" <linux-rdma@...r.kernel.org>,
"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: Aw: Re: RFC on writel and writel_relaxed
Hi,
>
> Yeah so that other trick I'm talking about is also used for timing
> accuracy.
>
> For example, let's say I have a device with a reset bit and the spec
> says the reset bit needs to be set for at least 10us.
>
> This is wrong:
>
> writel(1, RESET_REG);
> usleep(10);
> writel(0, RESET_REG);
>
> Because of write posting, the first write might arrive to the device
> right before the second one.
>
Does not write posting only concern PCI? This seems to be a different topic. Furthermore
write posting should not include write reordering...
Regards,
Lino
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