netdev - linux-next: manual merge of the net-next tree with the pci tree

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Message-ID: <20180403131454.4f9f032d@canb.auug.org.au>
Date:   Tue, 3 Apr 2018 13:14:54 +1000
From:   Stephen Rothwell <sfr@...b.auug.org.au>
To:     David Miller <davem@...emloft.net>,
        Networking <netdev@...r.kernel.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>
Cc:     Linux-Next Mailing List <linux-next@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Tariq Toukan <tariqt@...lanox.com>,
        Saeed Mahameed <saeedm@...lanox.com>,
        Tal Gilboa <talgi@...lanox.com>
Subject: linux-next: manual merge of the net-next tree with the pci tree

Hi all,

Today's linux-next merge of the net-next tree got a conflict in:

  drivers/net/ethernet/mellanox/mlx5/core/en_main.c

between commit:

  2907938d2375 ("net/mlx5e: Use pcie_bandwidth_available() to compute bandwidth")

from the pci tree and commit:

  0608d4dbaf4e ("net/mlx5e: Unify slow PCI heuristic")

from the net-next tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/net/ethernet/mellanox/mlx5/core/en_main.c
index 884337f88589,0aab3afc6885..000000000000
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
@@@ -3880,16 -4026,50 +4033,20 @@@ void mlx5e_build_default_indir_rqt(u32 
  		indirection_rqt[i] = i % num_channels;
  }
  
- static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
 -static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
 -{
 -	enum pcie_link_width width;
 -	enum pci_bus_speed speed;
 -	int err = 0;
 -
 -	err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
 -	if (err)
 -		return err;
 -
 -	if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
 -		return -EINVAL;
 -
 -	switch (speed) {
 -	case PCIE_SPEED_2_5GT:
 -		*pci_bw = 2500 * width;
 -		break;
 -	case PCIE_SPEED_5_0GT:
 -		*pci_bw = 5000 * width;
 -		break;
 -	case PCIE_SPEED_8_0GT:
 -		*pci_bw = 8000 * width;
 -		break;
 -	default:
 -		return -EINVAL;
 -	}
 -
 -	return 0;
 -}
 -
+ static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
  {
- 	return (link_speed && pci_bw &&
- 		(pci_bw < 40000) && (pci_bw < link_speed));
- }
+ 	u32 link_speed = 0;
+ 	u32 pci_bw = 0;
  
- static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
- {
- 	return !(link_speed && pci_bw &&
- 		 (pci_bw <= 16000) && (pci_bw < link_speed));
+ 	mlx5e_get_max_linkspeed(mdev, &link_speed);
 -	mlx5e_get_pci_bw(mdev, &pci_bw);
++	pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
+ 	mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
+ 			   link_speed, pci_bw);
+ 
+ #define MLX5E_SLOW_PCI_RATIO (2)
+ 
+ 	return link_speed && pci_bw &&
+ 		link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
  }
  
  void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)

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