netdev - Re: [1/4,RFCv2] net: phy: realtek: Support RTL8366RB variant

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Message-ID: <CACRpkdaKZC2YHYO_xLEtTB6DYW4FpapNBe4KQSCO57iHmCLZvw@mail.gmail.com>
Date:   Tue, 29 May 2018 22:01:14 +0200
From:   Linus Walleij <linus.walleij@...aro.org>
To:     Heiner Kallweit <hkallweit1@...il.com>
Cc:     Andrew Lunn <andrew@...n.ch>,
        Vivien Didelot <vivien.didelot@...oirfairelinux.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        netdev <netdev@...r.kernel.org>,
        OpenWrt Development List <openwrt-devel@...ts.openwrt.org>,
        LEDE Development List <lede-dev@...ts.infradead.org>,
        Antti Seppälä <a.seppala@...il.com>,
        Roman Yeryomin <roman@...em.lv>,
        Colin Leitner <colin.leitner@...glemail.com>,
        Gabor Juhos <juhosg@...nwrt.org>
Subject: Re: [1/4,RFCv2] net: phy: realtek: Support RTL8366RB variant

On Tue, May 29, 2018 at 8:51 PM, Heiner Kallweit <hkallweit1@...il.com> wrote:

>> +#define RTL8366RB_POWER_SAVE 0x21

> Typically PHY register addresses are 5 bits wide, is 0x21 correct
> and I miss something?

If it is correct I don't know, but it appears in the vendor
code:

/*Power Saving*/
#define RTL8368S_POWER_SAVING_PAGE                              0
#define RTL8368S_POWER_SAVING_REG                                       21
#define RTL8368S_POWER_SAVING_BIT_MSK                   0x1000

Then:

        phySmiAddr = 0x8000 | (1<<(phyNo +RTL8368S_PHY_NO_OFFSET)) |

((RTL8368S_POWER_SAVING_PAGE<<RTL8368S_PHY_PAGE_OFFSET)&RTL8368S_PHY_PAGE_MASK)
|
                        (RTL8368S_POWER_SAVING_REG&RTL8368S_PHY_REG_MASK);

        retVal = rtl8368s_setAsicReg(phySmiAddr, 0);
        if (retVal !=  SUCCESS)
                return retVal;

The PHYs are accessed here in memory area 0x8000.

Fixed the rest, thanks!

Yours,
Linus Walleij