netdev - Re: [1/4,RFCv2] net: phy: realtek: Support RTL8366RB variant

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Message-ID: <20180529201754.GE13697@lunn.ch>
Date:   Tue, 29 May 2018 22:17:54 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Linus Walleij <linus.walleij@...aro.org>
Cc:     Heiner Kallweit <hkallweit1@...il.com>,
        Vivien Didelot <vivien.didelot@...oirfairelinux.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        netdev <netdev@...r.kernel.org>,
        OpenWrt Development List <openwrt-devel@...ts.openwrt.org>,
        LEDE Development List <lede-dev@...ts.infradead.org>,
        Antti Seppälä <a.seppala@...il.com>,
        Roman Yeryomin <roman@...em.lv>,
        Colin Leitner <colin.leitner@...glemail.com>,
        Gabor Juhos <juhosg@...nwrt.org>
Subject: Re: [1/4,RFCv2] net: phy: realtek: Support RTL8366RB variant

On Tue, May 29, 2018 at 10:01:14PM +0200, Linus Walleij wrote:
> On Tue, May 29, 2018 at 8:51 PM, Heiner Kallweit <hkallweit1@...il.com> wrote:
> 
> >> +#define RTL8366RB_POWER_SAVE 0x21
> 
> > Typically PHY register addresses are 5 bits wide, is 0x21 correct
> > and I miss something?

Heiner is correct, MDIO only supports 32 register, when using clause
22. However, your device is not clause 22, it is its own thing. So one
danger you have is that we put some checks in the generic code testing
for values > 31, and return -EINVAL.

I think you have two choices:

1) A comment explaining what is going on here, how 0x21 is valid in
this context. And check the return value and give out a good warning
which will point somebody in the right direction to notice this 0x21.

2) Move this into the DSA driver, which does not have this
restriction.

	Andrew