netdev - Re: [PATCH 0/4 RFCv2] Realtek SMI RTL836x DSA driver

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Message-ID: <20180529122424.GC10919@lunn.ch>
Date:   Tue, 29 May 2018 14:24:24 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Linus Walleij <linus.walleij@...aro.org>
Cc:     Vivien Didelot <vivien.didelot@...oirfairelinux.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        netdev <netdev@...r.kernel.org>,
        OpenWrt Development List <openwrt-devel@...ts.openwrt.org>,
        LEDE Development List <lede-dev@...ts.infradead.org>
Subject: Re: [PATCH 0/4 RFCv2] Realtek SMI RTL836x DSA driver

On Tue, May 29, 2018 at 10:49:46AM +0200, Linus Walleij wrote:
> On Mon, May 28, 2018 at 8:20 PM, Andrew Lunn <andrew@...n.ch> wrote:
> > On Mon, May 28, 2018 at 07:47:48PM +0200, Linus Walleij wrote:
> >> This is a second RFC version of the DSA driver for Realtek
> >> RTL8366x especially RTL8366RB.
> >>
> >> I've been beating my head against this one and I'm not really
> >> clear on why my ethernet frames are not coming through to the
> >> CPU port on the chip.
> >>
> >> It appears when using ethtool -S on the ports that packets
> >> are passing fine into the router fabric and through to the
> >> CPU port but the ethernet driver where the fixed link is
> >> connected refuse to accept the packages.
> >
> > Hi Linus
> >
> > Have you played with RGMII delays?
> 
> No not like I changed them or anything... the SoC has some
> set-up for skew and delay on the nanosecond level, but I used the
> vendor defaults, verified to be the same in their custom
> kernel tree.

Hi Linus

Did you look at the switch end? I found a datasheet for the
8366/8369. Register at 0x0050, P8GCR. It has two bits for RGMII
delays.

With RGMII delays, you have 3 'choices'.

1) The hardware design includes the delay, by zig-zagging the clock
line to make it longer.
2) The 'MAC' side does the delay.
3) The 'PHY' side does the delay.

I normally recommend the PHY side doing it, because that's what most
board do. Gives us some consistency. But it does not really
matter. Just make sure one side, and only once side is inserting the
delays.

	Andrew