netdev - Re: [PATCH 3/3 v2] net: dsa: Add Vitesse VSC73xx DSA router driver

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Message-Id: <20180704.113240.652641829194832375.davem@davemloft.net>
Date:   Wed, 04 Jul 2018 11:32:40 +0900 (KST)
From:   David Miller <davem@...emloft.net>
To:     linus.walleij@...aro.org
Cc:     andrew@...n.ch, vivien.didelot@...oirfairelinux.com,
        f.fainelli@...il.com, netdev@...r.kernel.org,
        openwrt-devel@...ts.openwrt.org, lede-dev@...ts.infradead.org,
        juhosg@...nwrt.org
Subject: Re: [PATCH 3/3 v2] net: dsa: Add Vitesse VSC73xx DSA router driver

From: Linus Walleij <linus.walleij@...aro.org>
Date: Sat, 30 Jun 2018 13:17:31 +0200

> This adds a DSA driver for:
> 
> Vitesse VSC7385 SparX-G5 5-port Integrated Gigabit Ethernet Switch
> Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
> Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
> Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
> 
> These switches have a built-in 8051 CPU and can download and execute
> firmware in this CPU. They can also be configured to use an external
> CPU handling the switch in a memory-mapped manner by connecting to
> that external CPU's memory bus.
> 
> This driver (currently) only takes control of the switch chip over
> SPI and configures it to route packages around when connected to a
> CPU port. The chip has embedded PHYs and VLAN support so we model it
> using DSA as a best fit so we can easily add VLAN support and maybe
> later also exploit the internal frame header to get more direct
> control over the switch.
> 
> The four built-in GPIO lines are exposed using a standard GPIO chip.
> 
> Signed-off-by: Linus Walleij <linus.walleij@...aro.org>
> ---
> ChangeLog v1->v2:
> - Update .get_strings() and .get_sset_count() to match the signature
>   with the new argument for sset type.
> - Drop DSA trailer select from Kconfig.
> - Use MII_* namespace definitions instead of hard-coded hex
>   values and calls to read into the PHY: instead use the genphy
>   decoded link state already present in the phydev.
> - Drop extraneous port number check in .enable() and .disable(),
>   this should not happen.
> - Move the GPIO chip set-up into a separate function.
> - Add some missing static in front of a counter function.
> - Drop the bool flags in the state container, use some macros with
>   the chipid to identify model instead like IS_VSC739X().
> - Check phydev->interface() for configuring the CPU port into
>   RGMII mode.

Applied.