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Message-ID: <153539541079.129321.16889319226246451527@swboyd.mtv.corp.google.com>
Date:   Mon, 27 Aug 2018 11:43:30 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     "David S . Miller" <davem@...emloft.net>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        Hans de Goede <hdegoede@...hat.com>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Irina Tirdea <irina.tirdea@...el.com>,
        Michael Turquette <mturquette@...libre.com>
Cc:     Hans de Goede <hdegoede@...hat.com>, netdev@...r.kernel.org,
        Johannes Stezenbach <js@...21.net>,
        Carlo Caione <carlo@...lessm.com>, linux-clk@...r.kernel.org
Subject: Re: [PATCH 1/4] clk: x86: add "ether_clk" alias for Bay Trail / Cherry Trail

Quoting Hans de Goede (2018-08-27 07:31:57)
> Commit d31fd43c0f9a ("clk: x86: Do not gate clocks enabled by the
> firmware") causes all unclaimed PMC clocks on Cherry Trail devices to be on
> all the time, resulting on the device not being able to reach S0i2 or S0i3
> when suspended.
> 
> The reason for this commit is that on some Bay Trail / Cherry Trail devices
> the ethernet controller uses pmc_plt_clk_4. This commit adds an "ether_clk"
> alias, so that the relevant ethernet drivers can try to (optionally) use
> this, without needing X86 specific code / hacks, thus fixing ethernet on
> these devices without breaking S0i3 support.
> 
> This commit uses clkdev_hw_create() to create the alias, mirroring the code
> for the already existing "mclk" alias for pmc_plt_clk_3.
> 
> Buglink: https://bugzilla.kernel.org/show_bug.cgi?id=193891#c102
> Cc: Johannes Stezenbach <js@...21.net>
> Cc: Carlo Caione <carlo@...lessm.com>
> Signed-off-by: Hans de Goede <hdegoede@...hat.com>
> ---

Acked-by: Stephen Boyd <sboyd@...nel.org>

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