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Message-ID: <417caa76-2f37-d220-fb52-326529eb83af@c-s.fr>
Date: Wed, 29 Aug 2018 09:09:56 +0200
From: Christophe LEROY <christophe.leroy@....fr>
To: David Gounaris <david.gounaris@...inera.com>, qiang.zhao@....com,
netdev@...r.kernel.org, linuxppc-dev@...ts.ozlabs.org
Subject: Re: [PATCH 1/6] net/wan/fsl_ucc_hdlc: allow ucc index up to 4
Le 28/08/2018 à 15:34, Christophe LEROY a écrit :
>
>
> Le 28/08/2018 à 13:09, David Gounaris a écrit :
>> There is a need to allow higher indexes to be
>> able to support MPC83xx platforms. (UCC1-UCC5)
>
> As far as I can see, MPC8358 has 8 UCCs (ref
> https://www.nxp.com/products/processors-and-microcontrollers/power-architecture-processors/powerquicc-processors/powerquicc-ii-pro/powerquicc-ii-pro-processor-with-ddr2-tdm-pci-security-usb-quicc-engine-with-1-gb-ethernet-utopia:MPC8358E)
Indeed, the code should use UCC_MAX_NUM which is defined in
include/soc/fsl/qe/ucc.h
Christophe
>
>
> Christophe
>
>>
>> Signed-off-by: David Gounaris <david.gounaris@...inera.com>
>> ---
>> drivers/net/wan/fsl_ucc_hdlc.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/wan/fsl_ucc_hdlc.c
>> b/drivers/net/wan/fsl_ucc_hdlc.c
>> index 5f0366a125e2..3c0e0a1d19ba 100644
>> --- a/drivers/net/wan/fsl_ucc_hdlc.c
>> +++ b/drivers/net/wan/fsl_ucc_hdlc.c
>> @@ -1015,7 +1015,7 @@ static int ucc_hdlc_probe(struct platform_device
>> *pdev)
>> }
>> ucc_num = val - 1;
>> - if ((ucc_num > 3) || (ucc_num < 0)) {
>> + if ((ucc_num > 4) || (ucc_num < 0)) {
>> dev_err(&pdev->dev, ": Invalid UCC num\n");
>> return -EINVAL;
>> }
>>
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