netdev - Re: [PATCH 6/7] MIPS: mscc: add DT for Ocelot PCB120

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20180914145853.GR14988@piout.net>
Date:   Fri, 14 Sep 2018 16:58:53 +0200
From:   Alexandre Belloni <alexandre.belloni@...tlin.com>
To:     Quentin Schulz <quentin.schulz@...tlin.com>
Cc:     ralf@...ux-mips.org, paul.burton@...s.com, jhogan@...nel.org,
        robh+dt@...nel.org, mark.rutland@....com, davem@...emloft.net,
        andrew@...n.ch, f.fainelli@...il.com, allan.nielsen@...rochip.com,
        linux-mips@...ux-mips.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
        thomas.petazzoni@...tlin.com, antoine.tenart@...tlin.com
Subject: Re: [PATCH 6/7] MIPS: mscc: add DT for Ocelot PCB120

On 14/09/2018 11:44:27+0200, Quentin Schulz wrote:
> The Ocelot PCB120 evaluation board is different from the PCB123 in that
> it has 4 external VSC8584 (or VSC8574) PHYs.
> 
> It uses the SoC's second MDIO bus for external PHYs which have a
> reversed address on the bus (i.e. PHY4 is on address 3, PHY5 is on
> address 2, PHY6 on 1 and PHY7 on 0).
> 
> Here is how the PHYs are connected to the switch ports:
> port 0: phy0 (internal)
> port 1: phy1 (internal)
> port 2: phy2 (internal)
> port 3: phy3 (internal)
> port 4: phy7
> port 5: phy4
> port 6: phy6
> port 9: phy5
> 
> Signed-off-by: Quentin Schulz <quentin.schulz@...tlin.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@...tlin.com>

> ---
>  arch/mips/boot/dts/mscc/Makefile          |   2 +-
>  arch/mips/boot/dts/mscc/ocelot_pcb120.dts | 100 +++++++++++++++++++++++-
>  2 files changed, 101 insertions(+), 1 deletion(-)
>  create mode 100644 arch/mips/boot/dts/mscc/ocelot_pcb120.dts
> 
> diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
> index 9a9bb7e..ec6f5b2 100644
> --- a/arch/mips/boot/dts/mscc/Makefile
> +++ b/arch/mips/boot/dts/mscc/Makefile
> @@ -1,3 +1,3 @@
> -dtb-$(CONFIG_MSCC_OCELOT)	+= ocelot_pcb123.dtb
> +dtb-$(CONFIG_MSCC_OCELOT)	+= ocelot_pcb123.dtb ocelot_pcb120.dtb
>  
>  obj-$(CONFIG_BUILTIN_DTB)	+= $(addsuffix .o, $(dtb-y))
> diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
> new file mode 100644
> index 0000000..8eb03a5
> --- /dev/null
> +++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
> @@ -0,0 +1,100 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2017 Microsemi Corporation */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/phy/phy-ocelot-serdes.h>
> +#include "ocelot.dtsi"
> +
> +/ {
> +	compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory@0 {
> +		device_type = "memory";
> +		reg = <0x0 0x0e000000>;
> +	};
> +};
> +
> +&mdio0 {
> +	status = "okay";
> +};
> +
> +&mdio1 {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&miim1>, <&gpio4>;
> +
> +	phy7: ethernet-phy@0 {
> +		reg = <0>;
> +		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-parent = <&gpio>;
> +	};
> +	phy6: ethernet-phy@1 {
> +		reg = <1>;
> +		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-parent = <&gpio>;
> +	};
> +	phy5: ethernet-phy@2 {
> +		reg = <2>;
> +		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-parent = <&gpio>;
> +	};
> +	phy4: ethernet-phy@3 {
> +		reg = <3>;
> +		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-parent = <&gpio>;
> +	};
> +};
> +
> +&port0 {
> +	phy-handle = <&phy0>;
> +};
> +
> +&port1 {
> +	phy-handle = <&phy1>;
> +};
> +
> +&port2 {
> +	phy-handle = <&phy2>;
> +};
> +
> +&port3 {
> +	phy-handle = <&phy3>;
> +};
> +
> +&port4 {
> +	phy-handle = <&phy7>;
> +	phy-mode = "sgmii";
> +	phys = <&serdes 4 SERDES1G_2>;
> +};
> +
> +&port5 {
> +	phy-handle = <&phy4>;
> +	phy-mode = "sgmii";
> +	phys = <&serdes 5 SERDES1G_5>;
> +};
> +
> +&port6 {
> +	phy-handle = <&phy6>;
> +	phy-mode = "sgmii";
> +	phys = <&serdes 6 SERDES1G_3>;
> +};
> +
> +&port9 {
> +	phy-handle = <&phy5>;
> +	phy-mode = "sgmii";
> +	phys = <&serdes 9 SERDES1G_4>;
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&uart2 {
> +	status = "okay";
> +};
> -- 
> git-series 0.9.1

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com