netdev - Re: [PATCH v3 net-next] ravb: do not write 1 to reserved bits

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20180918.201026.764474223291614125.davem@redhat.com>
Date:   Tue, 18 Sep 2018 20:10:26 -0700 (PDT)
From:   David Miller <davem@...hat.com>
To:     horms+renesas@...ge.net.au
Cc:     sergei.shtylyov@...entembedded.com, magnus.damm@...il.com,
        netdev@...r.kernel.org, linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH v3 net-next] ravb: do not write 1 to reserved bits

From: Simon Horman <horms+renesas@...ge.net.au>
Date: Tue, 18 Sep 2018 12:22:26 +0200

> From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@...esas.com>
> 
> EtherAVB hardware requires 0 to be written to status register bits in
> order to clear them, however, care must be taken not to:
> 
> 1. Clear other bits, by writing zero to them
> 2. Write one to reserved bits
> 
> This patch corrects the ravb driver with respect to the second point above.
> This is done by defining reserved bit masks for the affected registers and,
> after auditing the code, ensure all sites that may write a one to a
> reserved bit use are suitably masked.
> 
> Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@...esas.com>
> Signed-off-by: Simon Horman <horms+renesas@...ge.net.au>

I've decided to apply this to 'net', let me know if this is a problem.