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Message-Id: <20180919.211345.499002396520654228.davem@davemloft.net>
Date: Wed, 19 Sep 2018 21:13:45 -0700 (PDT)
From: David Miller <davem@...emloft.net>
To: antoine.tenart@...tlin.com
Cc: netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
thomas.petazzoni@...tlin.com, maxime.chevallier@...tlin.com,
gregory.clement@...tlin.com, miquel.raynal@...tlin.com,
nadavh@...vell.com, stefanc@...vell.com, ymarkman@...vell.com,
mw@...ihalf.com
Subject: Re: [PATCH net-next 00/12] net: mvpp2: improve the interrupt usage
From: Antoine Tenart <antoine.tenart@...tlin.com>
Date: Wed, 19 Sep 2018 11:26:59 +0200
> This series aims to improve the interrupts descriptions and usage in the
> Marvell PPv2 driver.
>
> - Before the series interrupts were named after their s/w usage,
> which in fact can be configured. The series rename all those
> interrupts and add a description of the ones left over.
>
> - In PPv2 the interrupts are mapped to vectors. Those vectors were
> directly mapped to a given CPU, and per-cpu accesses were done. While
> this worked on our cases, the registers accesses mapped to the vectors
> are not actually linked to a given CPU. They instead are linked to
> what is called a "s/w thread". The series modify this so that the s/w
> threads are used instead of the CPU numbers, by adding an indirection.
> This means we now can have systems with more CPUs than s/w threads.
>
> This is based on today's net-next, and was tested on various boards
> using both versions of the PPv2 engine.
>
> Two more patches will be coming, to update the device trees describing a
> PPv2 engine. The patches are ready, but will go through a different
> tree. I'll send them once this series will be accepted. This is not an
> issue as the PPv2 driver keeps the dt bindings backward compatibility.
Series applied, thanks Antoine.
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