netdev - Re: [PATCH bpf] mips: bpf: fix encoding bug for mm_srlv32

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Message-ID: <99d47574-5a9a-4a43-5f90-e44712d0b124@netronome.com>
Date:   Mon, 3 Dec 2018 22:07:10 +0000
From:   Jiong Wang <jiong.wang@...ronome.com>
To:     Paul Burton <paul.burton@...s.com>
Cc:     "daniel@...earbox.net" <daniel@...earbox.net>,
        "ast@...nel.org" <ast@...nel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "oss-drivers@...ronome.com" <oss-drivers@...ronome.com>,
        Markos Chandras <markos.chandras@...tec.com>
Subject: Re: [PATCH bpf] mips: bpf: fix encoding bug for mm_srlv32_op

On 03/12/2018 22:04, Paul Burton wrote:
> Hi Jiong,
>
> On Sat, Dec 01, 2018 at 04:10:01AM -0500, Jiong Wang wrote:
>> For micro-mips, srlv inside POOL32A encoding space should use 0x50
>> sub-opcode, NOT 0x90.
>>
>> Some early version ISA doc describes the encoding as 0x90 for both srlv and
>> srav, this looks to me was a typo. I checked Binutils libopcode
>> implementation which is using 0x50 for srlv and 0x90 for srav.
> Are you aware of documentation that gets this right?

No, I am not aware of.

> Looking at the
> latest microMIPS spec I have available (6.05) it looks like this is
> still documented incorrectly. I'll pass this along to the architecture
> team.
>
>> Fixes: f31318fdf324 ("MIPS: uasm: Add srlv uasm instruction")
>> CC: Markos Chandras <markos.chandras@...tec.com>
>> CC: Paul Burton <paul.burton@...s.com>
>> Acked-by: Jakub Kicinski <jakub.kicinski@...ronome.com>
>> Signed-off-by: Jiong Wang <jiong.wang@...ronome.com>
>> ---
>>   arch/mips/include/uapi/asm/inst.h | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
>> index c05dcf5..80f35e7 100644
>> --- a/arch/mips/include/uapi/asm/inst.h
>> +++ b/arch/mips/include/uapi/asm/inst.h
>> @@ -370,7 +370,7 @@ enum mm_32a_minor_op {
>>   	mm_pool32axf_op = 0x03c,
>>   	mm_srl32_op = 0x040,
>>   	mm_sra_op = 0x080,
>> -	mm_srlv32_op = 0x090,
>> +	mm_srlv32_op = 0x050,
>>   	mm_rotr_op = 0x0c0,
>>   	mm_lwxs_op = 0x118,
>>   	mm_addu32_op = 0x150,
> Could you also move it above mm_sra_op to keep them sorted by value?
>
> When submitting v2 please also copy the linux-mips mailing list -
> linux-mips@...r.kernel.org.

Thanks, will do.

Regards,
Jiong