netdev - Re: [RFC bpf-next 1/7] bpf: interpreter support BPF_ALU

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Message-ID: <20181204201602.w5frlyy6ccsv47i4@ast-mbp.dhcp.thefacebook.com>
Date:   Tue, 4 Dec 2018 12:16:04 -0800
From:   Alexei Starovoitov <alexei.starovoitov@...il.com>
To:     David Miller <davem@...emloft.net>
Cc:     jiong.wang@...ronome.com, daniel@...earbox.net, ast@...nel.org,
        netdev@...r.kernel.org, oss-drivers@...ronome.com
Subject: Re: [RFC bpf-next 1/7] bpf: interpreter support BPF_ALU | BPF_ARSH

On Tue, Dec 04, 2018 at 12:10:05PM -0800, David Miller wrote:
> From: Alexei Starovoitov <alexei.starovoitov@...il.com>
> Date: Tue, 4 Dec 2018 11:29:55 -0800
> 
> > I guess sparc doesn't really have 32 subregisters.  All registers
> > are considered 64-bit. It has 32-bit alu ops on 64-bit registers
> > instead.
> 
> Right.
> 
> Anyways, sparc will require two instructions because of this, the
> 'sra' then a 'srl' by zero bits to clear the top 32-bits.
> 
> I'll code up the sparc JIT part when this goes in.

You already did :)
As far as I can see sparc64 JIT supports it properly.
Just like x64.
Hence the patches for these JITs are missing in Joing's set.