netdev - Re: [RFC bpf-next 1/7] bpf: interpreter support BPF_ALU

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Message-Id: <20181204.121940.1747647536236768664.davem@davemloft.net>
Date:   Tue, 04 Dec 2018 12:19:40 -0800 (PST)
From:   David Miller <davem@...emloft.net>
To:     jiong.wang@...ronome.com
Cc:     alexei.starovoitov@...il.com, daniel@...earbox.net, ast@...nel.org,
        netdev@...r.kernel.org, oss-drivers@...ronome.com
Subject: Re: [RFC bpf-next 1/7] bpf: interpreter support BPF_ALU | BPF_ARSH

From: Jiong Wang <jiong.wang@...ronome.com>
Date: Tue, 4 Dec 2018 20:14:11 +0000

> On 04/12/2018 20:10, David Miller wrote:
>> From: Alexei Starovoitov <alexei.starovoitov@...il.com>
>> Date: Tue, 4 Dec 2018 11:29:55 -0800
>>
>>> I guess sparc doesn't really have 32 subregisters.  All registers
>>> are considered 64-bit. It has 32-bit alu ops on 64-bit registers
>>> instead.
>> Right.
>>
>> Anyways, sparc will require two instructions because of this, the
>> 'sra' then a 'srl' by zero bits to clear the top 32-bits.
>>
>> I'll code up the sparc JIT part when this goes in.
> 
> Hmm, I had been going through all JIT backends, and saw there is
> do_alu32_trunc after jitting sra for BPF_ALU. That's what needed?

Yes, it clears the top 32-bits of a register after a 32-bit
ALU op beccause BPF's semantics require it.

In fact, we call it too much, we even call it for 32-bit
shift right instructions which automatically clear those
top bits.  I've been meaning to optimize that.

Meanwhile, again the answer to your question is yes.