lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 05 Dec 2018 11:28:32 +0000
From:   Jiong Wang <jiong.wang@...ronome.com>
To:     Sandipan Das <sandipan@...ux.ibm.com>
Cc:     Jiong Wang <jiong.wang@...ronome.com>, daniel@...earbox.net,
        ast@...nel.org, netdev@...r.kernel.org, oss-drivers@...ronome.com,
        "Naveen N . Rao" <naveen.n.rao@...ux.ibm.com>
Subject: Re: [PATCH bpf-next 2/7] ppc: bpf: implement jitting of BPF_ALU | BPF_ARSH | BPF_*


Sandipan Das writes:

> Hi Jiong,
>
> On 05/12/18 2:25 AM, Jiong Wang wrote:
>> This patch implements code-gen for BPF_ALU | BPF_ARSH | BPF_*.
>> 
>> Cc: Naveen N. Rao <naveen.n.rao@...ux.ibm.com>
>> Cc: Sandipan Das <sandipan@...ux.ibm.com>
>> Signed-off-by: Jiong Wang <jiong.wang@...ronome.com>
>> ---
> [...]
>> diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_comp64.c
>> index 17482f5..c685b4f 100644
>> --- a/arch/powerpc/net/bpf_jit_comp64.c
>> +++ b/arch/powerpc/net/bpf_jit_comp64.c
>> @@ -529,9 +529,15 @@ static int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
>>  			if (imm != 0)
>>  				PPC_SRDI(dst_reg, dst_reg, imm);
>>  			break;
>> +		case BPF_ALU | BPF_ARSH | BPF_X: /* (s32) dst >>= src */
>> +			PPC_SRAW(dst_reg, dst_reg, src_reg);
>> +			break;
>
> On ppc64, the sraw and srawi instructions also use sign extension. So, you will have
> to ensure that upper 32 bits are cleared. We already have a label in our JIT code
> called bpf_alu32_trunc that takes care of this. Replacing the break statement with
> a goto bpf_alu32_trunc will fix this.

(resend the reply, got a delivery failure notification from
netdev@...r.kernel.org)

Indeed. Doubled checked the ISA doc,"Bit 32 of RS is replicated to fill
RA0:31.".

Will fix both places in v2.

Thanks

Regards,
Jiong

>
>>  		case BPF_ALU64 | BPF_ARSH | BPF_X: /* (s64) dst >>= src */
>>  			PPC_SRAD(dst_reg, dst_reg, src_reg);
>>  			break;
>> +		case BPF_ALU | BPF_ARSH | BPF_K: /* (s32) dst >>= imm */
>> +			PPC_SRAWI(dst_reg, dst_reg, imm);
>> +			break;
>
> Same here.
>
>>  		case BPF_ALU64 | BPF_ARSH | BPF_K: /* (s64) dst >>= imm */
>>  			if (imm != 0)
>>  				PPC_SRADI(dst_reg, dst_reg, imm);
>> 
>
> With Regards,
> Sandipan

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ