netdev - [PATCH 7/7] net: dsa: qca8k: handle disable tx/rx delay

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20190102091729.18582-8-vkoul@kernel.org>
Date:   Wed,  2 Jan 2019 14:47:29 +0530
From:   Vinod Koul <vkoul@...nel.org>
To:     "David S . Miller" <davem@...emloft.net>
Cc:     netdev@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        Niklas Cassel <niklas.cassel@...aro.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Vinod Koul <vkoul@...nel.org>, Andrew Lunn <andrew@...n.ch>,
        Florian Fainelli <f.fainelli@...il.com>,
        Vivien Didelot <vivien.didelot@...oirfairelinux.com>
Subject: [PATCH 7/7] net: dsa: qca8k: handle disable tx/rx delay

We should disable tx/rx delay in rgmii mode, but driver doesn't do so.
Hence add a device tree property to avoid breaking current users and
disable only when this property is set

<Fixme: change author to ...>
Signed-off-by: Vinod Koul <vkoul@...nel.org>
---
 drivers/net/dsa/qca8k.c | 27 ++++++++++++++++++---------
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 7e97e620bd44..6dfb390ebe66 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -420,7 +420,9 @@ qca8k_mib_init(struct qca8k_priv *priv)
 static int
 qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
 {
-	u32 reg;
+	u32 reg, val;
+	struct dsa_switch *ds = priv->ds;
+	bool rx_delay_disable, tx_delay_disable;
 
 	switch (port) {
 	case 0:
@@ -439,17 +441,24 @@ qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
 	 */
 	switch (mode) {
 	case PHY_INTERFACE_MODE_RGMII:
-		qca8k_write(priv, reg,
-			    QCA8K_PORT_PAD_RGMII_EN |
-			    QCA8K_PORT_PAD_RGMII_TX_DELAY(3) |
-			    QCA8K_PORT_PAD_RGMII_RX_DELAY(3));
-
-		/* According to the datasheet, RGMII delay is enabled through
+		rx_delay_disable = of_property_read_bool(ds->dst->cpu_dp->dn,
+							 "rx-delay-disable");
+		tx_delay_disable = of_property_read_bool(ds->dst->cpu_dp->dn,
+							 "tx-delay-disable");
+		val = QCA8K_PORT_PAD_RGMII_EN;
+		if (!rx_delay_disable)
+			val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(3);
+		if (!tx_delay_disable)
+			val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(3);
+		qca8k_write(priv, reg, val);
+
+		/* According to the datasheet, RGMII rx delay is enabled through
 		 * PORT5_PAD_CTRL for all ports, rather than individual port
 		 * registers
 		 */
-		qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
-			    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
+		if (!rx_delay_disable)
+			qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
+				    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
 		break;
 	case PHY_INTERFACE_MODE_SGMII:
 		qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
-- 
2.20.1