netdev - Re: [RFC PATCH 1/3] riscv: set HAVE_EFFICIENT_UNALIGNED

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Message-ID: <CAJ+HfNigethi_fK-Cv5CskH9B7b+9Go1_qSVsGhvXnX1kbxykw@mail.gmail.com>
Date:   Tue, 15 Jan 2019 17:06:47 +0100
From:   Björn Töpel <bjorn.topel@...il.com>
To:     Christoph Hellwig <hch@...radead.org>
Cc:     linux-riscv@...ts.infradead.org,
        Palmer Dabbelt <palmer@...ive.com>, davidlee@...ive.com,
        Daniel Borkmann <daniel@...earbox.net>,
        Netdev <netdev@...r.kernel.org>
Subject: Re: [RFC PATCH 1/3] riscv: set HAVE_EFFICIENT_UNALIGNED_ACCESS

Den tis 15 jan. 2019 kl 16:39 skrev Christoph Hellwig <hch@...radead.org>:
>
> Hmm, while the RISC-V spec requires misaligned load/store support,
> who says they are efficient?  Maybe add a little comment that says
> on which cpus they are efficient.

Good point! :-) I need to check how other architectures does this.
Enabling it for *all* RV64 is probably not correct.