netdev - Re: [PATCH net-next 8/8] net: mscc: PTP offloading support

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Message-ID: <20190118090841.GH25424@kwain>
Date:   Fri, 18 Jan 2019 10:08:41 +0100
From:   Antoine Tenart <antoine.tenart@...tlin.com>
To:     Richard Cochran <richardcochran@...il.com>
Cc:     Antoine Tenart <antoine.tenart@...tlin.com>, davem@...emloft.net,
        alexandre.belloni@...tlin.com, UNGLinuxDriver@...rochip.com,
        ralf@...ux-mips.org, paul.burton@...s.com, jhogan@...nel.org,
        netdev@...r.kernel.org, linux-mips@...r.kernel.org,
        thomas.petazzoni@...tlin.com, quentin.schulz@...tlin.com,
        allan.nielsen@...rochip.com
Subject: Re: [PATCH net-next 8/8] net: mscc: PTP offloading support

Hi Richard,

On Thu, Jan 17, 2019 at 06:23:43PM -0800, Richard Cochran wrote:
> On Thu, Jan 17, 2019 at 11:02:12AM +0100, Antoine Tenart wrote:
> > This patch adds support for offloading PTP timestamping to the Ocelot
> > switch for both 1-step and 2-step modes.
> 
> For PTP Hardware Clock drivers, please add the PTP maintainer onto CC.

Will do for the v2, sorry about that.

> > +static int ocelot_ptp_settime64(struct ptp_clock_info *ptp,
> > +				const struct timespec64 *ts)
> > +{
> > +	struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
> > +	u32 val;
> > +
> > +	val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
> > +	val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
> > +	val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE);
> > +
> > +	ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
> > +
> > +	ocelot_write_rix(ocelot, lower_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_LSB,
> > +			 TOD_ACC_PIN);
> > +	ocelot_write_rix(ocelot, upper_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_MSB,
> > +			 TOD_ACC_PIN);
> > +	ocelot_write_rix(ocelot, ts->tv_nsec, PTP_PIN_TOD_NSEC, TOD_ACC_PIN);
> > +
> > +	val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
> > +	val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
> > +	val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_LOAD);
> > +
> > +	ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
> 
> You are writing multiple registers.  This code is not safe when called
> concurrently.
> 
> Ditto for gettime, adjtime, and adjfreq.

Right, I'll fix that.

> > +static int ocelot_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
> > +{
> 
> Please implement adjfine instead.

OK, I'll look into it.

> > +	struct mutex ptp_lock;
> 
> Just what does this mutex protect?  Please add a comment.

OK.

Thanks!
Antoine

-- 
Antoine Ténart, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com