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Message-ID: <20190121132945.6e6dee23@bootlin.com> Date: Mon, 21 Jan 2019 13:29:45 +0100 From: Maxime Chevallier <maxime.chevallier@...tlin.com> To: Russell King - ARM Linux admin <linux@...linux.org.uk> Cc: Andrew Lunn <andrew@...n.ch>, davem@...emloft.net, netdev@...r.kernel.org, linux-kernel@...r.kernel.org, Florian Fainelli <f.fainelli@...il.com>, Heiner Kallweit <hkallweit1@...il.com>, linux-arm-kernel@...ts.infradead.org, Antoine Tenart <antoine.tenart@...tlin.com>, thomas.petazzoni@...tlin.com, gregory.clement@...tlin.com, miquel.raynal@...tlin.com, nadavh@...vell.com, stefanc@...vell.com, mw@...ihalf.com Subject: Re: [PATCH net-next 5/7] net: phy: marvell10g: Force reading of 2.5/5G PMA extended abilities Hello Russell, On Mon, 21 Jan 2019 10:52:06 +0000 Russell King - ARM Linux admin <linux@...linux.org.uk> wrote: >On Mon, Jan 21, 2019 at 11:35:31AM +0100, Maxime Chevallier wrote: >> Hello Andrew, >> >> On Sun, 20 Jan 2019 20:08:09 +0100 >> Andrew Lunn <andrew@...n.ch> wrote: >> >> >On Fri, Jan 18, 2019 at 04:23:50PM +0100, Maxime Chevallier wrote: >> >> As per 802.3bz, if bit 14 of (1.11) "PMA Extended Abilities" indicates >> >> whether or not we should read register (1.21) "2.52/5G PMA Extended >> >> Abilities", which contains information on the support of 2.5GBASET and >> >> 5GBASET. >> >> >> >> After testing on several variants of PHYS of this family, it appears >> >> that bit 14 in (1.11) isn't always set when it should be. >> >> >> >> PHYs 88X3310 (on MacchiatoBin) and 88E2010 do support 2.5G and 5GBASET, >> >> but don't have 1.11.14 set. Their register 1.21 is filled with the >> >> correct values, indicating 2.5G and 5G support. >> >> >> >> PHYs 88X2110 do have their 1.11.14 bit set, as it should. >> > >> >Hi Maxime >> > >> >Is there anything about this in any Errata? >> >> I haven't seen any Errata on that unfortunately. >> >> I also thought about reading (1.4) "PMA/PMD Speed Ability", but the >> 2.5G and 5G speeds are also reported as not being supported on the >> 88X3310. > >It's entirely possible that the 3310 switches to different hardware >blocks for 2.5G and 5G speeds, and reading _just_ the 1.4 register >is not sufficient. I agree with you but in that particular case, I think we are reading from the correct device. The datasheet itself says that we should be reading 1.4 and 1.11 as we expect, with 2.5G/5G support being set (these registers are read-only, and the datasheet's values aren't what we actually read). >The 88x3310 is multiple PHY devices in one package, with a CPU that >manages the routing between each individual device. I also just checked register 3.4 "PCS Speed Ability", and 3.8 "PCS Status 2" which also contains informations on 2.5G/5G abilities, but there's the same issue here. Maxime -- Maxime Chevallier, Bootlin Embedded Linux and kernel engineering https://bootlin.com
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