lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Mon, 4 Feb 2019 20:35:18 +0100
From:   Andrew Lunn <>
To:     John David Anglin <>
Cc:     Russell King <>,
        Vivien Didelot <>,
        Florian Fainelli <>,
Subject: Re: [PATCH] net: phylink: dsa: mv88e6xxx: Revise irq setup ordering

On Mon, Feb 04, 2019 at 01:37:13PM -0500, John David Anglin wrote:
> This change fixes a race condition in the setup of hardware irqs and the
> code enabling PHY link
> detection.
> This was observed on the espressobin board where the GPIO interrupt
> controller only supports edge
> interrupts.  If the INTn output pin goes low before the GPIO interrupt
> is enabled, PHY link interrupts
> are not detected.

Hi David

Please break this up into two patches.

Masking interrupts in the setup code before enabling the interrupt i'm
happy with.

The change to the interrupt handler i'm pretty sure is wrong. You have
to accept with edge interrupts you are going to loose interrupts.


Powered by blists - more mailing lists