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Date:   Wed, 20 Feb 2019 09:06:51 +0100
From:   Thomas Petazzoni <>
To:     Andrew Lunn <>
Cc:     Paul Kocialkowski <>,
        Florian Fainelli <>,
        Heiner Kallweit <>,,
        Mylène Josserand <>
Subject: Re: Handling an Extra Signal at PHY Reset

On Tue, 19 Feb 2019 14:36:29 +0100
Andrew Lunn <> wrote:

> This seems like an odd design. I've normally seen weak pull up/down
> resistors, not a switch, so i'm wondering why it is designed like
> this.

The key point here is that this "CONFIG" pin of the PHY is used during
reset to configure the PHY, but then once the reset sequence is
finished, this pin is used for PTP. From the datasheet, section 2.28.1
"PTP Control":

To support the PTP Time Stamping function, the device has four pins
that are global to the entire PHY:

- PTP clock input pin (The CONFIG pin is used for this purpose.)
- PTP Event Request input pin (The LED[1] pin is used for this purpose)
- PTP Event Request input pin (The LED[1] pin is used for this purpose)
- Interrupt Pin (The LED[2] pin is used for this purpose)

A bit further down in the datasheet:

"After configuration is completed and the external clock source is
enabled, the CONFIG pin is used as the external 125 Mhz reference clock

So that's why our design as a switch: it allows the CONFIG pin to be
used for configuration during the reset sequence, and then as the pin
for the PTP clock input.

Does that clarify why the CONFIG pin is not simply connected to some
static pull-up/pull-down ?

Best regards,

Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering

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