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Date:   Sun, 24 Feb 2019 21:56:46 +0100
From:   Maxime Chevallier <maxime.chevallier@...tlin.com>
To:     Heiner Kallweit <hkallweit1@...il.com>
Cc:     David Miller <davem@...emloft.net>, netdev@...r.kernel.org
Subject: Re: marvell10g.c merge into net-next

Hello Dave, Heiner,

On Sun, 24 Feb 2019 21:35:11 +0100
Heiner Kallweit <hkallweit1@...il.com> wrote:

>On 24.02.2019 21:15, David Miller wrote:
>> 
>> Heiner, please look at net-next which I just merged net into.
>> 
>> Net had a bug fix wherein the MDIO_AN_10GBT_CTRL_ADV_NBT_MASK
>> bits are cleared in the 10gbt control register to work around
>> a problem with some marvell10g phy chips.
>> 
>> In the merge I preserved your usage of the generic c45 helpers
>> in this area, but I suspect part of that will have to be undone
>> in order to accomodate the above fix.
>>   
>Thanks for the info. Let me add Maxime as author of the fix.
>I think we talk about his one "net: phy: marvell10g:
>Fix Multi-G advertisement to only advertise 10G" and we talk
>about net-next.
>
>IMO the proper way to fix this is removing the unsupported
>modes from phydev->advertising in config_init.
>Then mv3310_config_aneg doesn't have to be touched.
>
>A similar exercise I did here:
>0974f1f03b07 ("net: phy: aquantia: remove false 5G and 10G speed ability for AQCS109")

>From what I've seen and tested, the issue itself doesn't appear in
net-next, since mv3310_config_aneg calls the newly introduced
genphy_c45_an_config_aneg() which clears the 2.5G/5G advertising bits.

So the use of the generic C45 helpers should be enough to prevent the
issue from happening. The only difference really is that the -net patch
also masks the 2.5/5G Fast Retrain abilities, but this should make no
difference given that 2.5/5G are masked-out in both cases.

I'm sorry for the confusion, I wasn't sure how to deal with such a
scenario.

Thanks,

Maxime


-- 
Maxime Chevallier, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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