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Message-ID: <CO2PR07MB2469EC9B8761CE1DC45D6832C1470@CO2PR07MB2469.namprd07.prod.outlook.com>
Date: Mon, 18 Mar 2019 17:49:34 +0000
From: Parshuram Raju Thombare <pthombar@...ence.com>
To: Florian Fainelli <f.fainelli@...il.com>,
"andrew@...n.ch" <andrew@...n.ch>
CC: "nicolas.ferre@...rochip.com" <nicolas.ferre@...rochip.com>,
"davem@...emloft.net" <davem@...emloft.net>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
"hkallweit1@...il.com" <hkallweit1@...il.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Rafal Ciepiela <rafalc@...ence.com>,
Piotr Sroka <piotrs@...ence.com>, Jan Kotas <jank@...ence.com>
Subject: RE: [PATCH v2 2/3] net: ethernet: cadence: add c45 PHY support in
MDIO read/write functions.
Thanks for quick reply.
I am still working on other patches, so I think I will send all of them in another single mail chain.
Regards,
Parshuram Thombare
>-----Original Message-----
>From: Florian Fainelli <f.fainelli@...il.com>
>Sent: Monday, March 18, 2019 11:15 PM
>To: Parshuram Raju Thombare <pthombar@...ence.com>; andrew@...n.ch
>Cc: nicolas.ferre@...rochip.com; davem@...emloft.net;
>netdev@...r.kernel.org; hkallweit1@...il.com; linux-kernel@...r.kernel.org;
>Rafal Ciepiela <rafalc@...ence.com>; Piotr Sroka <piotrs@...ence.com>; Jan
>Kotas <jank@...ence.com>
>Subject: Re: [PATCH v2 2/3] net: ethernet: cadence: add c45 PHY support in MDIO
>read/write functions.
>
>EXTERNAL MAIL
>
>
>On 3/18/19 10:42 AM, Parshuram Thombare wrote:
>> Sorry for sending this patch again, but I didn't sent previous email
>> --in-reply-to last comment on v1 of this patch. So rectifying this
>> mistake.
>
>You have 3 patches in your series, you need to resend all of them even if there is
>only one to which you are making changes, this is not documented in netdev-
>FAQ.rst though, let's update that.
>
>>
>> This version 2 of patch to modify MDIO read/write functions to support
>> communication with C45 PHY in Cadence ethernet controller driver.
>>
>> Changes:
>> 1. Added timeout
>> 2. Removed unused operation macro
>MACB_MAN_C45_POST_READ_INCR
>>
>> I thought of starting with relatively smaller, independant and simpler changes.
>> This patch is independant of patch series and looks relatively
>> straight forward with aim of supporting C45 PHY for support of high speed
>PHY's.
>>
>> Signed-off-by: Parshuram Thombare <pthombar@...ence.com>
>> ---
>> drivers/net/ethernet/cadence/macb.h | 14 +++++--
>> drivers/net/ethernet/cadence/macb_main.c | 61
>++++++++++++++++++++++++-----
>> 2 files changed, 60 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/cadence/macb.h
>> b/drivers/net/ethernet/cadence/macb.h
>> index acc66a7..d25fa03 100644
>> --- a/drivers/net/ethernet/cadence/macb.h
>> +++ b/drivers/net/ethernet/cadence/macb.h
>> @@ -629,10 +629,16 @@
>> #define GEM_CLK_DIV96 5
>>
>> /* Constants for MAN register */
>> -#define MACB_MAN_SOF 1
>> -#define MACB_MAN_WRITE 1
>> -#define MACB_MAN_READ 2
>> -#define MACB_MAN_CODE 2
>> +#define MACB_MAN_C22_SOF 1
>> +#define MACB_MAN_C22_WRITE 1
>> +#define MACB_MAN_C22_READ 2
>> +#define MACB_MAN_C22_CODE 2
>> +
>> +#define MACB_MAN_C45_SOF 0
>> +#define MACB_MAN_C45_ADDR 0
>> +#define MACB_MAN_C45_WRITE 1
>> +#define MACB_MAN_C45_READ 3
>> +#define MACB_MAN_C45_CODE 2
>>
>> /* Capability mask bits */
>> #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
>> diff --git a/drivers/net/ethernet/cadence/macb_main.c
>> b/drivers/net/ethernet/cadence/macb_main.c
>> index ad099fd..17072fd 100644
>> --- a/drivers/net/ethernet/cadence/macb_main.c
>> +++ b/drivers/net/ethernet/cadence/macb_main.c
>> @@ -345,11 +345,30 @@ static int macb_mdio_read(struct mii_bus *bus, int
>mii_id, int regnum)
>> if (status < 0)
>> goto mdio_read_exit;
>>
>> - macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
>> - | MACB_BF(RW, MACB_MAN_READ)
>> - | MACB_BF(PHYA, mii_id)
>> - | MACB_BF(REGA, regnum)
>> - | MACB_BF(CODE, MACB_MAN_CODE)));
>> + if (regnum & MII_ADDR_C45) {
>> + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
>> + | MACB_BF(RW, MACB_MAN_C45_ADDR)
>> + | MACB_BF(PHYA, mii_id)
>> + | MACB_BF(REGA, (regnum >> 16) & 0x1F)
>> + | MACB_BF(DATA, regnum & 0xFFFF)
>> + | MACB_BF(CODE, MACB_MAN_C45_CODE)));
>> +
>> + status = macb_mdio_wait_for_idle(bp);
>> + if (status < 0)
>> + goto mdio_read_exit;
>> +
>> + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
>> + | MACB_BF(RW, MACB_MAN_C45_READ)
>> + | MACB_BF(PHYA, mii_id)
>> + | MACB_BF(REGA, (regnum >> 16) & 0x1F)
>> + | MACB_BF(CODE, MACB_MAN_C45_CODE)));
>> + } else {
>> + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
>> + | MACB_BF(RW, MACB_MAN_C22_READ)
>> + | MACB_BF(PHYA, mii_id)
>> + | MACB_BF(REGA, regnum)
>> + | MACB_BF(CODE, MACB_MAN_C22_CODE)));
>> + }
>>
>> status = macb_mdio_wait_for_idle(bp);
>> if (status < 0)
>> @@ -378,12 +397,32 @@ static int macb_mdio_write(struct mii_bus *bus, int
>mii_id, int regnum,
>> if (status < 0)
>> goto mdio_write_exit;
>>
>> - macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
>> - | MACB_BF(RW, MACB_MAN_WRITE)
>> - | MACB_BF(PHYA, mii_id)
>> - | MACB_BF(REGA, regnum)
>> - | MACB_BF(CODE, MACB_MAN_CODE)
>> - | MACB_BF(DATA, value)));
>> + if (regnum & MII_ADDR_C45) {
>> + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
>> + | MACB_BF(RW, MACB_MAN_C45_ADDR)
>> + | MACB_BF(PHYA, mii_id)
>> + | MACB_BF(REGA, (regnum >> 16) & 0x1F)
>> + | MACB_BF(DATA, regnum & 0xFFFF)
>> + | MACB_BF(CODE, MACB_MAN_C45_CODE)));
>> +
>> + status = macb_mdio_wait_for_idle(bp);
>> + if (status < 0)
>> + goto mdio_write_exit;
>> +
>> + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
>> + | MACB_BF(RW, MACB_MAN_C45_WRITE)
>> + | MACB_BF(PHYA, mii_id)
>> + | MACB_BF(REGA, (regnum >> 16) & 0x1F)
>> + | MACB_BF(CODE, MACB_MAN_C45_CODE)
>> + | MACB_BF(DATA, value)));
>> + } else {
>> + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
>> + | MACB_BF(RW, MACB_MAN_C22_WRITE)
>> + | MACB_BF(PHYA, mii_id)
>> + | MACB_BF(REGA, regnum)
>> + | MACB_BF(CODE, MACB_MAN_C22_CODE)
>> + | MACB_BF(DATA, value)));
>> + }
>>
>> status = macb_mdio_wait_for_idle(bp);
>> if (status < 0)
>>
>
>
>--
>Florian
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