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Message-ID: <871d452d-6e3f-d3ad-6434-e4b552ca37d5@gmail.com>
Date:   Sat, 23 Mar 2019 17:59:26 -0700
From:   Florian Fainelli <f.fainelli@...il.com>
To:     Heiner Kallweit <hkallweit1@...il.com>,
        Andrew Lunn <andrew@...n.ch>,
        David Miller <davem@...emloft.net>
Cc:     "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        Phil Reid <preid@...ctromag.com.au>,
        liweihang <liweihang@...ilicon.com>
Subject: Re: [PATCH net] net: phy: don't clear BMCR in genphy_soft_reset



On 3/22/2019 12:00 PM, Heiner Kallweit wrote:
> So far we effectively clear the BMCR register. Some PHY's can deal
> with this (e.g. because they reset BMCR to a default as part of a
> soft-reset) whilst on others this causes issues because e.g. the
> autoneg bit is cleared. Marvell is an example, see also thread [0].
> So let's be a little bit more gentle and leave all bits we're not
> interested in as-is. This change is needed for PHY drivers to
> properly deal with the original patch.
> 
> [0] https://marc.info/?t=155264050700001&r=1&w=2
> 
> Fixes: 6e2d85ec0559 ("net: phy: Stop with excessive soft reset")
> Tested-by: Phil Reid <preid@...ctromag.com.au>
> Tested-by: liweihang <liweihang@...ilicon.com>
> Signed-off-by: Heiner Kallweit <hkallweit1@...il.com>

Reviewed-by: Florian Fainelli <f.fainelli@...il.com>

Thanks for investigating and coming up with a fix for this!

> ---
>  drivers/net/phy/phy_device.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
> index 49fdd1ee7..77068c545 100644
> --- a/drivers/net/phy/phy_device.c
> +++ b/drivers/net/phy/phy_device.c
> @@ -1831,7 +1831,7 @@ int genphy_soft_reset(struct phy_device *phydev)
>  {
>  	int ret;
>  
> -	ret = phy_write(phydev, MII_BMCR, BMCR_RESET);
> +	ret = phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
>  	if (ret < 0)
>  		return ret;
>  
> 

-- 
Florian

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