netdev - Re: [net-next 13/15] net/mlx5: A write memory barrier is sufficient in EQ ci update

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Message-ID: <CALzJLG8af0SMfA1C8U8r_Fddb_ZQhvEZd6=2a97dOoBcgLA0xg@mail.gmail.com>
Date:   Fri, 5 Apr 2019 13:50:01 -0700
From:   Saeed Mahameed <saeedm@....mellanox.co.il>
To:     Gal Pressman <galpress@...zon.com>
Cc:     Saeed Mahameed <saeedm@...lanox.com>,
        Tariq Toukan <tariqt@...lanox.com>,
        "David S. Miller" <davem@...emloft.net>,
        Linux Netdev List <netdev@...r.kernel.org>
Subject: Re: [net-next 13/15] net/mlx5: A write memory barrier is sufficient
 in EQ ci update

On Thu, Apr 4, 2019 at 4:46 AM Gal Pressman <galpress@...zon.com> wrote:
>
> On 03-Apr-19 02:03, Saeed Mahameed wrote:
> > From: Tariq Toukan <tariqt@...lanox.com>
> >
> > Soften the memory barrier call of mb() by a sufficient wmb() in the
> > consumer index update of the event queues.
> >
> > Signed-off-by: Tariq Toukan <tariqt@...lanox.com>
> > Signed-off-by: Saeed Mahameed <saeedm@...lanox.com>
> > ---
> >  drivers/net/ethernet/mellanox/mlx5/core/eq.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c
> > index 46a747f7c162..e9837aeb7088 100644
> > --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c
> > +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c
> > @@ -707,7 +707,7 @@ void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm)
> >
> >       __raw_writel((__force u32)cpu_to_be32(val), addr);
> >       /* We still want ordering, just not swabbing, so add a barrier */
> > -     mb();
> > +     wmb();
>
> Shouldn't this barrier be placed prior to __raw_writel()?

same effect in both cases, we just want a fence between every two
consecutive writes.