lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Sat, 27 Apr 2019 10:44:01 +0300
From:   Serge Semin <fancer.lancer@...il.com>
To:     Florian Fainelli <f.fainelli@...il.com>
Cc:     Andrew Lunn <andrew@...n.ch>,
        Heiner Kallweit <hkallweit1@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Serge Semin <Sergey.Semin@...latforms.ru>,
        netdev@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/2] net: phy: realtek: Add rtl8211e rx/tx delays
 config

On Fri, Apr 26, 2019 at 08:11:50PM -0700, Florian Fainelli wrote:
> 
> 
> On 4/26/2019 4:45 PM, Serge Semin wrote:
> > On Fri, Apr 26, 2019 at 11:40:50PM +0200, Andrew Lunn wrote:
> >> On Sat, Apr 27, 2019 at 12:21:11AM +0300, Serge Semin wrote:
> >>> There are two chip pins named TXDLY and RXDLY which actually adds the 2ns
> >>> delays to TXC and RXC for TXD/RXD latching. Alas this is the only
> >>> documented info regarding the RGMII timing control configurations the PHY
> >>> provides. It turns out the same settings can be setup via MDIO registers
> >>> hidden in the extension pages layout. Particularly the extension page 0xa4
> >>> provides a register 0x1c, which bits 1 and 2 control the described delays.
> >>> They are used to implement the "rgmii-{id,rxid,txid}" phy-mode.
> >>>
> >>> The hidden RGMII configs register utilization was found in the rtl8211e
> >>> U-boot driver:
> >>> https://elixir.bootlin.com/u-boot/v2019.01/source/drivers/net/phy/realtek.c#L99
> >>>
> >>> There is also a freebsd-folks discussion regarding this register:
> >>> https://reviews.freebsd.org/D13591
> >>>
> >>> It confirms that the register bits field must control the so called
> >>> configuration pins described in the table 12-13 of the official PHY
> >>> datasheet:
> >>> 8:6 = PHY Address
> >>> 5:4 = Auto-Negotiation
> >>> 3 = Interface Mode Select
> >>> 2 = RX Delay
> >>> 1 = TX Delay
> >>> 0 = SELRGV
> >>>
> >>> Signed-off-by: Serge Semin <fancer.lancer@...il.com>
> >>
> >>
> >> Hi Serge
> >>
> >> Next time please include a patch 0 containing a cover note explaining
> >> the who series.
> >>
> > 
> > Sure as long as the patchset gets to be much bigger than two small
> > patches with an obvious reason to be merged.
> 
> netdev likes to have a cover letter for patch count >= 1, probably
> something to be added to netdev-FAQ.rst.
> -- 
> Florian

Hello Florian
Really, even with count = 1? So just one patch with cover-letter? Doesn't it
seem redundant since at least a single patch can be thoroughly described in
it' commit message?

-Sergey

Powered by blists - more mailing lists