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Date: Sat, 27 Apr 2019 17:35:56 +0200 From: Andrew Lunn <andrew@...n.ch> To: Igor Russkikh <Igor.Russkikh@...antia.com> Cc: "David S . Miller" <davem@...emloft.net>, "netdev@...r.kernel.org" <netdev@...r.kernel.org>, Nikita Danilov <Nikita.Danilov@...antia.com>, Dmitry Bogdanov <Dmitry.Bogdanov@...antia.com> Subject: Re: [PATCH v3 net-next 14/15] net: aquantia: fixups on 64bit dma counters On Sat, Apr 27, 2019 at 06:28:12AM +0000, Igor Russkikh wrote: > > > On 27.04.2019 0:36, Andrew Lunn wrote: > >> + self->curr_stats.dma_pkt_rc = hw_atl_stats_rx_dma_good_pkt_counterlsw_get(self) + > >> + ((u64)hw_atl_stats_rx_dma_good_pkt_countermsw_get(self) << 32); > > > > Don't you need to do something to avoid issue with overflow from lsw > > into msw? I've often seen code get the msw, the lsw and then the msm > > again. If the two msw reads are different, it repeats it all again. > > Hardware latches msw when host reads lsw register. So thats safe. > > However looking into spec it says to always read lsw first. > The syntax above does not guarantee that in general. > I'll change that with something like > > dma_pkt_rc = hw_atl_stats_rx_dma_good_pkt_counterlsw_get(self); > dma_pkt_rc |= ((u64)hw_atl_stats_rx_dma_good_pkt_countermsw_get(self) << 32); Hi Igor I think i would probably have a hw_atl_stats_rx_dma_good_pkt_counter() which returns a u64. Under that, have a aq_hw_read_reg64() which does things in the correct ordering, and a comment about reading the lsw latches the msw. Andrew
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