netdev - Re: DSA setup IMX6ULL and Marvell 88E6390 with 2 Ethernet Phys

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Date:   Thu, 23 May 2019 07:52:38 +0200
From:   Benjamin Beckmeyer <beb@...-engel.de>
To:     Andrew Lunn <andrew@...n.ch>
CC:     <netdev@...r.kernel.org>
Subject: Re: DSA setup IMX6ULL and Marvell 88E6390 with 2 Ethernet Phys - CPU
 Port is not working


On 22.05.19 18:32, Andrew Lunn wrote:
> On Wed, May 22, 2019 at 10:33:29AM +0200, Benjamin Beckmeyer wrote:
>> Hi all,
>>
>> I'm currently working on a custom board with the imx6ull processor and the 6390 
>> switching chip. This is our hardware setup. 
>>
>> ------------     ---------         ---------    MAC     ------------
>> |   i.MX   | MAC |  PHY  |   PHY   |  PHY  |------------|  88E6390 |
>> |   6ULL   |-----|KSZ8081|---------|LAN8742|	MDIO	|P0        |
>> |          |     |ID 0x1 |         | ID0x0 |------------|          |
>> |          |     ---------         ---------            |          |
>> |          |	     |                                  |MULTI CHIP|
>> |          |	     |MDIO                              |ADDR MODE |
>> |          |	     |                                  |          |
>> |          |--------------------------------------------|   PHY ID |
>> |          |                    MDIO                    |     0x2  |
>> ------------						------------
> Hi Benjamin
>
> KSZ8081 is a 10/100 PHY, i think.
> LAN8742 is also a 10/100 PHY.
>
> However, DSA will configure the CPU port MAC to its maximum speed. So
> port 0 will be doing 1G. I don't know if specifying phy-mode = "rmii"
> is enough. You should take a look at the port status and configuration
> registers, see if the MAC is being forced to 1G, or 100M.
>
> You could add a fixed-phy to port 0 with speed 100. That will at least
> get the MAC part configured correctly.
>
> Is the LAN8742 strapped so that on power on it will auto-neg? I've
> seen a few board with this back-to-back PHY setup, and they just rely
> on the PHYs doing the right thing on power up, no software involved.
>
>    Andrew

Good morning Andrew,
thanks for your reply. You're right, both PHYs are 10/100.

I already added a fixed-link like this:

			port@0 {
				reg = <0>;
				label = "cpu";
				ethernet = <&fec1>;
				phy-mode = "rmii";
				phy-handle = <&switch0phy0>;
                                fixed-link {
                                        speed = <100>;
                                        full-duplex;
                                };
			};

I hope you mean that with fixed-phy? But this doesn't changed anything.

I would like to look at the port registers, but how can I read it when DSA 
is started? When I delete the whole DSA part from the devicetree I found the 
switch in multi chip addressing mode and can read the registers per indirect
reads from PHY ID 0x2. But when DSA is initialized our MII tool(which tool 
could I use for that? ethtool?) gives back some odd values. Of course, I 
would like to read it when DSA is running.

We will check the strapping again, because we have a strange behavior. On 
some boots the external MDIO found a PHY at PHY ID 0x0 and on some it found
nothing. 

Thanks,
Benjamin