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Message-ID: <47108d803086402c83d1073f3e3a62bb@escrypt.com>
Date:   Fri, 16 Aug 2019 08:26:16 +0000
From:   "FIXED-TERM Buecheler Konstantin (ETAS-SEC/ECT-Mu)" 
        <fixed-term.Konstantin.Buecheler@...rypt.com>
To:     Patrick Menschel <menschel.p@...teo.de>,
        Marc Kleine-Budde <mkl@...gutronix.de>,
        "linux-can@...r.kernel.org" <linux-can@...r.kernel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>
CC:     Dan Murphy <dmurphy@...com>
Subject: AW: can: tcan4x5x: spi bits_per_word issue on Raspberry PI

> >> Now I have another really confusing problem. Anything I write to SPI is written little endian. The tcan chip expects big endian.
> >> Anything I read from SPI is treated as little endian but is big endian. Does anyone know why this happens?
> >> Is there a flag or something I can set for the SPI device/wire to fix this?
> >
> > Have you changed the bits_per_word to 8? Then you read just a stream
> > of bytes. If you tread them as an u32 they are in host order.
> >

@Marc
Yes, I changed bits_per_word to 8. Since the PI does not support any values apart from 
8 and 9 this seems to be the only way.

> > Marc
> >
> 
> 
> Hi,
> 
> from my experience with SPIDEV on RPI, the driver uses a char array for I/O.
> As the RPI code is build little endian, logically little endian comes out of SPI. You
> basically have to invert the bit and byte order by hand for a big endian slave.
> 

@Patrick, Marc
You both are right. This seems to be the problem. The SPI driver uses char arrays
and the tcan driver treats them as u32. 

I will try to change the byte order by hand to get it running for my project. But in the long 
run, this does not seem to be a proper solution... 

Regards, 
Konstantin 


> Clock Phase and Clock Polarity are also an issue on the RPI as at least SPIDEV
> kindly overlooks any options set previously.
> I had my share of this while writing a test app for a MAX31855 IC and ended up
> casting a little endian array to a big endian structure.
> 
> Regards,
> Patrick

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