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Message-ID: <VI1PR04MB48805CB7B660EADD62BA347196B10@VI1PR04MB4880.eurprd04.prod.outlook.com>
Date: Wed, 11 Sep 2019 16:01:45 +0000
From: Claudiu Manoil <claudiu.manoil@....com>
To: Andrew Lunn <andrew@...n.ch>
CC: "David S . Miller" <davem@...emloft.net>,
Alexandru Marginean <alexandru.marginean@....com>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: RE: [PATCH net-next 1/5] enetc: Fix if_mode extraction
>-----Original Message-----
>From: Andrew Lunn <andrew@...n.ch>
>Sent: Tuesday, September 10, 2019 10:44 AM
>To: Claudiu Manoil <claudiu.manoil@....com>
>Cc: David S . Miller <davem@...emloft.net>; Alexandru Marginean
><alexandru.marginean@....com>; netdev@...r.kernel.org
>Subject: Re: [PATCH net-next 1/5] enetc: Fix if_mode extraction
>
>On Mon, Sep 09, 2019 at 04:24:01PM +0000, Claudiu Manoil wrote:
[...]
>>
>> Hi Andrew,
>>
>> The MAC2MAC connections are defined as fixed-link too, but without
>> phy-mode/phy-connection-type properties. We don't want to de-register
>> these links. Initial code was bogus in this regard.
>
>Hi Claudiu
>
>This is what is not clear in the change log. That this code is removed
>because it is wrong. Please could you expand the explanation to make
>this clearer.
>
I agree, but I also need to modify the patch to handle both the error case
of invalid phy-mode for mdio and normal fixed link phy connections, and
the mac2mac connection case. The mac2mac connection case can be also
deferred to a later patch, when the switch driver - Felix - will be available
(there's no use for it in the current enetc upstream driver).
>> Current proposal is:
>> ethernet@0,2 { /* SoC internal, connected to switch port 4 */
>> compatible = "fsl,enetc";
>> reg = <0x000200 0 0 0 0>;
>> fixed-link {
>> speed = <1000>;
>> full-duplex;
>> };
>> };
>> switch@0,5 {
>> compatible = "mscc,felix-switch";
>> [...]
>> ports {
>> #address-cells = <1>;
>> #size-cells = <0>;
>>
>> /* external ports */
>> [...]
>> /* internal SoC ports */
>> port@4 { /* connected to ENETC port2 */
>> reg = <4>;
>> fixed-link {
>> speed = <1000>;
>> full-duplex;
>> };
>> };
>
>So this connection between the SoC and the switch does not use tags?
>Can it use tags? Does the hardware allow you to have two CPU ports,
>and load balance over them?
>
Unfortunately the switch can handle only one port with tags. There's only
one CPU port, switch port 4 is just like another front panel port. On top of
that, the CPU port is not capable of flow control (pause frames don't work with
tagged traffic on the switch side). So we may be forced to use port 4 to mitigate
this. Note that the switch is inside the SoC.
>This second half is just standard DSA. This looks good.
>
Thanks for the confirmation and the rest of the review, all valid findings.
Regards,
Claudiu
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