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Date:   Thu, 10 Oct 2019 19:37:15 +0300
From:   Sergei Shtylyov <sergei.shtylyov@...entembedded.com>
To:     Thomas Bogendoerfer <tbogendoerfer@...e.de>,
        Jakub Kicinski <jakub.kicinski@...ronome.com>,
        Jonathan Corbet <corbet@....net>,
        Ralf Baechle <ralf@...ux-mips.org>,
        Paul Burton <paul.burton@...s.com>,
        James Hogan <jhogan@...nel.org>,
        Lee Jones <lee.jones@...aro.org>,
        "David S. Miller" <davem@...emloft.net>,
        Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
        Alessandro Zummo <a.zummo@...ertech.it>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Jiri Slaby <jslaby@...e.com>, linux-doc@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-mips@...r.kernel.org,
        netdev@...r.kernel.org, linux-rtc@...r.kernel.org,
        linux-serial@...r.kernel.org
Subject: Re: [PATCH v9 5/5] MIPS: SGI-IP27: Enable ethernet phy on second
 Origin 200 module

On 10/10/2019 05:59 PM, Thomas Bogendoerfer wrote:

> PROM only enables ethernet PHY on first Origin 200 module, so we must
> do it ourselves for the second module.
> 
> Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@...e.de>
> ---
>  arch/mips/pci/pci-ip27.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
> index 441eb9383b20..7cc784cb299b 100644
> --- a/arch/mips/pci/pci-ip27.c
> +++ b/arch/mips/pci/pci-ip27.c
> @@ -7,6 +7,11 @@
>   * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@...ux-mips.org)
>   * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
>   */
> +#include <asm/sn/addrs.h>
> +#include <asm/sn/types.h>
> +#include <asm/sn/klconfig.h>
> +#include <asm/sn/hub.h>
> +#include <asm/sn/ioc3.h>
>  #include <asm/pci/bridge.h>
>  
>  dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
> @@ -31,3 +36,20 @@ int pcibus_to_node(struct pci_bus *bus)
>  }
>  EXPORT_SYMBOL(pcibus_to_node);
>  #endif /* CONFIG_NUMA */
> +
> +static void ip29_fixup_phy(struct pci_dev *dev)
> +{
> +	int nasid = pcibus_to_node(dev->bus);
> +	u32 sid;
> +
> +	if (nasid != 1)
> +		return; /* only needed on second module */
> +
> +	/* enable ethernet PHY on IP29 systemboard */
> +	pci_read_config_dword(dev, PCI_SUBSYSTEM_VENDOR_ID, &sid);
> +	if (sid == ((PCI_VENDOR_ID_SGI << 16) | IOC3_SUBSYS_IP29_SYSBOARD))

   I thought PCI was little endian, thuis vendor ID at offset 0 and device ID
at offset 2?

[...]

MBR, Sergei

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