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Message-ID: <20191015134522.6002d501@cakuba.netronome.com>
Date: Tue, 15 Oct 2019 13:45:22 -0700
From: Jakub Kicinski <jakub.kicinski@...ronome.com>
To: Jiri Pirko <jiri@...nulli.us>
Cc: netdev@...r.kernel.org, davem@...emloft.net, andrew@...n.ch,
f.fainelli@...il.com, hkallweit1@...il.com, mlxsw@...lanox.com
Subject: Re: [patch net-next v2 0/2] mlxsw: Add support for 400Gbps (50Gbps
per lane) link modes
On Tue, 15 Oct 2019 22:14:16 +0200, Jiri Pirko wrote:
> Tue, Oct 15, 2019 at 09:07:57PM CEST, jakub.kicinski@...ronome.com wrote:
> >On Sat, 12 Oct 2019 18:27:56 +0200, Jiri Pirko wrote:
> >> From: Jiri Pirko <jiri@...lanox.com>
> >>
> >> Add 400Gbps bits to ethtool and introduce support in mlxsw. These modes
> >> are supported by the Spectrum-2 switch ASIC.
> >
> >Thanks for the update, looks good to me!
> >
> >Out of curiosity - why did we start bunching up LR, ER and FR?
>
> No clue. But it's been done like that for other speeds too.
Looks like for 50G Serdeses and 4x25G we started grouping by Clause.
Probably makes sense.
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