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Date:   Fri, 13 Dec 2019 17:04:20 +0100
From:   Antoine Tenart <antoine.tenart@...tlin.com>
To:     Russell King <rmk+kernel@...linux.org.uk>
Cc:     Andrew Lunn <andrew@...n.ch>,
        Florian Fainelli <f.fainelli@...il.com>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Antoine Tenart <antoine.tenart@...tlin.com>,
        "David S. Miller" <davem@...emloft.net>, netdev@...r.kernel.org
Subject: Re: [PATCH net-next 3/3] net: mvpp2: update mvpp2 validate()
 implementation

Hello Russell,

On Thu, Dec 12, 2019 at 05:43:46PM +0000, Russell King wrote:
> 
> diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> index 111b3b8239e1..fddd856338b4 100644
> --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> @@ -4786,6 +4786,8 @@ static void mvpp2_phylink_validate(struct phylink_config *config,
>  			phylink_set(mask, 10000baseER_Full);
>  			phylink_set(mask, 10000baseKR_Full);
>  		}
> +		if (state->interface != PHY_INTERFACE_MODE_NA)
> +			break;

>  		/* Fall-through */
>  	case PHY_INTERFACE_MODE_RGMII:
>  	case PHY_INTERFACE_MODE_RGMII_ID:
> @@ -4796,13 +4798,21 @@ static void mvpp2_phylink_validate(struct phylink_config *config,
>  		phylink_set(mask, 10baseT_Full);
>  		phylink_set(mask, 100baseT_Half);
>  		phylink_set(mask, 100baseT_Full);
> +		if (state->interface != PHY_INTERFACE_MODE_NA)
> +			break;

The two checks above will break the 10G/1G interfaces on the mcbin
(eth0/eth1) as they can support both 10gbase-kr and 10/100/1000baseT
modes depending on what's connected. With this patch only the modes
related to the one defined in the device tree would be valid, breaking
run-time reconfiguration of the link.

Thanks,
Antoine

-- 
Antoine Ténart, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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