netdev - Re: [PATCH net] net: dsa: sja1105: Take PTP egress timestamp by port, not mgmt slot

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Date:   Mon, 30 Dec 2019 20:11:00 -0800 (PST)
From:   David Miller <davem@...emloft.net>
To:     olteanv@...il.com
Cc:     jakub.kicinski@...ronome.com, richardcochran@...il.com,
        f.fainelli@...il.com, vivien.didelot@...il.com, andrew@...n.ch,
        netdev@...r.kernel.org
Subject: Re: [PATCH net] net: dsa: sja1105: Take PTP egress timestamp by
 port, not mgmt slot

From: Vladimir Oltean <olteanv@...il.com>
Date: Fri, 27 Dec 2019 02:59:54 +0200

> The PTP egress timestamp N must be captured from register PTPEGR_TS[n],
> where n = 2 * PORT + TSREG. There are 10 PTPEGR_TS registers, 2 per
> port. We are only using TSREG=0.
> 
> As opposed to the management slots, which are 4 in number
> (SJA1105_NUM_PORTS, minus the CPU port). Any management frame (which
> includes PTP frames) can be sent to any non-CPU port through any
> management slot. When the CPU port is not the last port (#4), there will
> be a mismatch between the slot and the port number.
> 
> Luckily, the only mainline occurrence with this switch
> (arch/arm/boot/dts/ls1021a-tsn.dts) does have the CPU port as #4, so the
> issue did not manifest itself thus far.
> 
> Fixes: 47ed985e97f5 ("net: dsa: sja1105: Add logic for TX timestamping")
> Signed-off-by: Vladimir Oltean <olteanv@...il.com>

Applied, thanks.