netdev - RE: [PATCH net-next 0/2] Fix 10G PHY interface types

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Message-ID: <DB8PR04MB698518D97251CB15938279C3EC230@DB8PR04MB6985.eurprd04.prod.outlook.com>
Date:   Fri, 3 Jan 2020 16:33:05 +0000
From:   "Madalin Bucur (OSS)" <madalin.bucur@....nxp.com>
To:     Andrew Lunn <andrew@...n.ch>,
        "Madalin Bucur (OSS)" <madalin.bucur@....nxp.com>
CC:     Russell King - ARM Linux admin <linux@...linux.org.uk>,
        Florian Fainelli <f.fainelli@...il.com>,
        Heiner Kallweit <hkallweit1@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Jonathan Corbet <corbet@....net>,
        Kishon Vijay Abraham I <kishon@...com>,
        "linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: RE: [PATCH net-next 0/2] Fix 10G PHY interface types

> -----Original Message-----
> From: Andrew Lunn <andrew@...n.ch>
> Sent: Friday, January 3, 2020 4:18 PM
> To: Madalin Bucur (OSS) <madalin.bucur@....nxp.com>
> Cc: Russell King - ARM Linux admin <linux@...linux.org.uk>; Florian
> Fainelli <f.fainelli@...il.com>; Heiner Kallweit <hkallweit1@...il.com>;
> David S. Miller <davem@...emloft.net>; Jonathan Corbet <corbet@....net>;
> Kishon Vijay Abraham I <kishon@...com>; linux-doc@...r.kernel.org;
> netdev@...r.kernel.org
> Subject: Re: [PATCH net-next 0/2] Fix 10G PHY interface types
> 
> > Describing the actual interface at chip to chip level (RGMII, SGMII,
> XAUI,
> > XFI, etc.). This may be incomplete for people trying to configure their
> HW
> > that supports multiple modes (reminder - device trees describe HW, they
> do
> > not configure SW). More details would be required and the list would
> be...
> > eclectic.
> 
> Hi Madalin
> 
> Please forget the existing DT binding for the moment. Please describe
> what values you need to program into your hardware to make it
> work. Please don't use the existing DT naming when describing what you
> need. Maybe use the terms from the reference manual?

Here is a PHY family document mentioning XFI:

https://www.marvell.com/documents/o67oxbpfhwx806cawedj/

And here is a LS1046A SoC document that describes XFI and 10GBASE_KR:

https://www.mouser.com/pdfdocs/LS1046A.pdf

(see sections 3.10.3 and 3.10.4).

> Once we have a list, we can figure out what could be generic, what
> could be vendor specific, and how to describe it in ACPI, DT, etc.
> 
> At LPC 2019, Claudiu and Vladimir talked about wanting to describe the
> eye configuration for some hardware. It would be interesting if there
> is any overlap. Aquantia also have some values used to configure the
> SERDES of their PHYs. I think this is a board specific binary blob
> which is loaded into the PHY as part of the firmware. That then limits
> their firmware to a specific board, which is not so nice. But does
> that also indicate that how the MAC is configured might also depend on
> how the PHY configures its electrical properties?
> 
>     Andrew

There are several NXP engineers addressing related issues, there is a vast
networking SoC family to support, with a large set of features, ranging
from the tried and true PPC SoCs to the new and feature rich ARM based SoC
that boast 1/2.5/10/40G Ethernet, backplane, TSN and so on. The PHY area
is often an excursion outside the direct area of responsibility but we need
to do this to get the complete systems working. Often the PHYs we use are
not as well supported upstream as we'd need so we have to get involved.

Regards,
Madalin