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Date:   Sat, 4 Jan 2020 23:04:55 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Vladimir Oltean <olteanv@...il.com>
Cc:     David Miller <davem@...emloft.net>,
        netdev <netdev@...r.kernel.org>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Chris Healy <Chris.Healy@....aero>
Subject: Re: [PATCH net] net: dsa: mv88e6xxx: Preserve priority went setting
 CPU port.

On Sat, Jan 04, 2020 at 08:56:12PM +0200, Vladimir Oltean wrote:
> Hi Andrew,
> 
> Is there a typo in the commit message? (went -> when)

Yep. Thanks for pointing it out.

> 
> On Sat, 4 Jan 2020 at 18:16, Andrew Lunn <andrew@...n.ch> wrote:
> >
> > The 6390 family uses an extended register to set the port connected to
> > the CPU. The lower 5 bits indicate the port, the upper three bits are
> > the priority of the frames as they pass through the switch, what
> > egress queue they should use, etc. Since frames being set to the CPU
> > are typically management frames, BPDU, IGMP, ARP, etc set the priority
> > to 7, the reset default, and the highest.
> >
> > Fixes: 33641994a676 ("net: dsa: mv88e6xxx: Monitor and Management tables")
> > Signed-off-by: Andrew Lunn <andrew@...n.ch>
> > ---
> 
> Offtopic: Does the switch look at VLAN PCP for these frames at all, or
> is the priority fixed to the value from this register?

I _think_ it is fixed. But this is just for "management"
frames. Normal data frames heading to the CPU because of MAC address
learning should have all the normal QoS operations the switch supports
to determining their priority.

> >  drivers/net/dsa/mv88e6xxx/global1.c | 5 +++++
> >  drivers/net/dsa/mv88e6xxx/global1.h | 1 +
> >  2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/net/dsa/mv88e6xxx/global1.c b/drivers/net/dsa/mv88e6xxx/global1.c
> > index 120a65d3e3ef..ce03f155e9fb 100644
> > --- a/drivers/net/dsa/mv88e6xxx/global1.c
> > +++ b/drivers/net/dsa/mv88e6xxx/global1.c
> > @@ -360,6 +360,11 @@ int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
> >  {
> >         u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
> >
> > +       /* Use the default high priority for manegement frames sent to
> 
> management

Humm. What happened to my spell checker?

> > +        * the CPU.
> > +        */
> > +       port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;
> > +
> >         return mv88e6390_g1_monitor_write(chip, ptr, port);
> >  }
> >
> > diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h
> > index bc5a6b2bb1e4..5324c6f4ae90 100644
> > --- a/drivers/net/dsa/mv88e6xxx/global1.h
> > +++ b/drivers/net/dsa/mv88e6xxx/global1.h
> > @@ -211,6 +211,7 @@
> >  #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST         0x2000
> >  #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST          0x2100
> >  #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST             0x3000
> > +#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI     0x00e0
> 
> I suppose this could be more nicely expressed as
> MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI(x)    ((x) << 5 &
> GENMASK(7, 5)), in case somebody wants to change it from 7?

It could be. But i'm not aware of any suitable existing API to
configure this. So i went KISS and used the hard coded value.

	  Andrew

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