netdev - RE: [PATCH net-next 0/2] Fix 10G PHY interface types

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Message-ID: <DB8PR04MB6985B617539D2E909B30822FEC3C0@DB8PR04MB6985.eurprd04.prod.outlook.com>
Date:   Mon, 6 Jan 2020 09:16:40 +0000
From:   "Madalin Bucur (OSS)" <madalin.bucur@....nxp.com>
To:     Andrew Lunn <andrew@...n.ch>,
        "Madalin Bucur (OSS)" <madalin.bucur@....nxp.com>
CC:     Russell King - ARM Linux admin <linux@...linux.org.uk>,
        Florian Fainelli <f.fainelli@...il.com>,
        Heiner Kallweit <hkallweit1@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Jonathan Corbet <corbet@....net>,
        Kishon Vijay Abraham I <kishon@...com>,
        "linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: RE: [PATCH net-next 0/2] Fix 10G PHY interface types

> -----Original Message-----
> From: Andrew Lunn <andrew@...n.ch>
> Sent: Friday, January 3, 2020 6:48 PM
> To: Madalin Bucur (OSS) <madalin.bucur@....nxp.com>
> Cc: Russell King - ARM Linux admin <linux@...linux.org.uk>; Florian
> Fainelli <f.fainelli@...il.com>; Heiner Kallweit <hkallweit1@...il.com>;
> David S. Miller <davem@...emloft.net>; Jonathan Corbet <corbet@....net>;
> Kishon Vijay Abraham I <kishon@...com>; linux-doc@...r.kernel.org;
> netdev@...r.kernel.org
> Subject: Re: [PATCH net-next 0/2] Fix 10G PHY interface types
> 
> > And here is a LS1046A SoC document that describes XFI and 10GBASE_KR:
> >
> > https://www.mouser.com/pdfdocs/LS1046A.pdf

You need to register, unfortunately, but the information is in the reference
manual (18.3 MB of download):

https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/qoriq-layerscape-1046a-and-1026a-multicore-communications-processors:LS1046A?tab=Documentation_Tab

You can find there also an application note on the backplane ethernet
support on this device, with a description of the current solution, describing
the SoC internal PCS (manageable through an MDIO bus) as a PHY to be able
to use the PHYlib infrastructure to control it. The code is still under
refinement, not upstream yet, but it's available and in use by customers.

> I don't see any register descriptions here. So you failed to answer my
> question. What do you actually need to configure? What needs to go
> into DT?
> 
> You keep avoiding the questions Russell and I pose, which is not
> helping your argument. We need details, not hand waiving.
> 
> 	Andrew

Answers are there, spreading the conversation on multiple threads and
removing history is not helping.

Madalin