netdev - Re: [PATCH] net: dsa: mv88e6xxx: don't force settings on CPU port

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Message-ID: <7a777bc3-9109-153a-a735-e36718c06db5@zonque.org>
Date:   Mon, 30 Mar 2020 20:04:08 +0200
From:   Daniel Mack <daniel@...que.org>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     vivien.didelot@...il.com, f.fainelli@...il.com,
        davem@...emloft.net, netdev@...r.kernel.org
Subject: Re: [PATCH] net: dsa: mv88e6xxx: don't force settings on CPU port

Hi Andrew,

Thanks for all your input.

On 3/30/20 3:40 PM, Andrew Lunn wrote:
> On Mon, Mar 30, 2020 at 11:29:27AM +0200, Daniel Mack wrote:
>> On 3/28/20 12:52 AM, Andrew Lunn wrote:

>>> By explicitly saying there is a PHY for the CPU node, phylink might
>>> drive it.
> 
> You want to debug this. Although what you have is unusual, yours is
> not the only board. It is something we want to work. And ideally,
> there should be something controlling the PHY.

I agree, but what I believe is happening here is this. The PHY inside
the switch negotiates a link to the 'external' PHY which is forced to
100M maximum speed. That link seems to work fine; the LEDs connected to
that external PHY indicate that there is link. However, the internal PHY
in the switch does not receive any packets as the MAC connected to it
only wants to communicate with 1G.

Not sure what else could be done other than allowing for reduced speed
on the MAC as well, which is what my patch is doing. I agree that my
approach falls short for boards where there is no PHY on the port
connected to the CPU, but maybe there is some common ground here, and a
rule can be defined under which circumstances the MAC speed should be
forced?

Thanks,
Daniel