netdev - Re: [PATCH] net: dsa: mv88e6xxx: don't force settings on CPU port

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Date:   Mon, 30 Mar 2020 20:37:00 +0200
From:   Daniel Mack <daniel@...que.org>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     vivien.didelot@...il.com, f.fainelli@...il.com,
        davem@...emloft.net, netdev@...r.kernel.org
Subject: Re: [PATCH] net: dsa: mv88e6xxx: don't force settings on CPU port

On 3/30/20 8:23 PM, Andrew Lunn wrote:
> On Mon, Mar 30, 2020 at 08:04:08PM +0200, Daniel Mack wrote:
>> Hi Andrew,
>>
>> Thanks for all your input.
>>
>> On 3/30/20 3:40 PM, Andrew Lunn wrote:
>>> On Mon, Mar 30, 2020 at 11:29:27AM +0200, Daniel Mack wrote:
>>>> On 3/28/20 12:52 AM, Andrew Lunn wrote:
>>
>>>>> By explicitly saying there is a PHY for the CPU node, phylink might
>>>>> drive it.
>>>
>>> You want to debug this. Although what you have is unusual, yours is
>>> not the only board. It is something we want to work. And ideally,
>>> there should be something controlling the PHY.
>>
>> I agree, but what I believe is happening here is this. The PHY inside
>> the switch negotiates a link to the 'external' PHY which is forced to
>> 100M maximum speed. That link seems to work fine; the LEDs connected to
>> that external PHY indicate that there is link. However, the internal PHY
>> in the switch does not receive any packets as the MAC connected to it
>> only wants to communicate with 1G.
> 
> Which is what phylink is all about. phylink will talk to the PHY,
> figure out what it has negotiated, and then configure the MAC to
> fit. So you need to debug why this is not happening.

Even when the MAC is *forced* to 1G, which is what the code currently
does? Sorry for the dumb question, but wich code path would undo these
settings? Where would you start debugging this?


Thanks,
Daniel