netdev - Re: [PATCH v1] net: phy: micrel: kszphy_resume(): add delay after genphy

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Message-Id: <20200403.160507.1105430274883121139.davem@davemloft.net>
Date:   Fri, 03 Apr 2020 16:05:07 -0700 (PDT)
From:   David Miller <davem@...emloft.net>
To:     o.rempel@...gutronix.de
Cc:     andrew@...n.ch, f.fainelli@...il.com, hkallweit1@...il.com,
        david@...tonic.nl, kernel@...gutronix.de,
        linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
        philippe.schenker@...adex.com, linux@...linux.org.uk
Subject: Re: [PATCH v1] net: phy: micrel: kszphy_resume(): add delay after
 genphy_resume() before accessing PHY registers

From: Oleksij Rempel <o.rempel@...gutronix.de>
Date: Fri,  3 Apr 2020 09:53:25 +0200

> After the power-down bit is cleared, the chip internally triggers a
> global reset. According to the KSZ9031 documentation, we have to wait at
> least 1ms for the reset to finish.
> 
> If the chip is accessed during reset, read will return 0xffff, while
> write will be ignored. Depending on the system performance and MDIO bus
> speed, we may or may not run in to this issue.
> 
> This bug was discovered on an iMX6QP system with KSZ9031 PHY and
> attached PHY interrupt line. If IRQ was used, the link status update was
> lost. In polling mode, the link status update was always correct.
> 
> The investigation showed, that during a read-modify-write access, the
> read returned 0xffff (while the chip was still in reset) and
> corresponding write hit the chip _after_ reset and triggered (due to the
> 0xffff) another reset in an undocumented bit (register 0x1f, bit 1),
> resulting in the next write being lost due to the new reset cycle.
> 
> This patch fixes the issue by adding a 1...2 ms sleep after the
> genphy_resume().
> 
> Fixes: 836384d2501d ("net: phy: micrel: Add specific suspend")
> Signed-off-by: Oleksij Rempel <o.rempel@...gutronix.de>

Applied and queued up for -stable, thank you.