netdev - Re: [RFC PATCH 0/3] net: macb: Wake-on-Lan magic packet fixes

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Message-ID: <CAFcVECLHkLSa+PaRWyoiqfYBpNNY3to-TSE3sqWPY3hY2chrXg@mail.gmail.com>
Date:   Mon, 6 Apr 2020 20:22:28 +0530
From:   Harini Katakam <harinik@...inx.com>
To:     Nicolas Ferre <nicolas.ferre@...rochip.com>
Cc:     linux-arm-kernel@...ts.infradead.org, netdev@...r.kernel.org,
        Claudiu Beznea <claudiu.beznea@...rochip.com>,
        Harini Katakam <harini.katakam@...inx.com>,
        linux-kernel@...r.kernel.org,
        "David S. Miller" <davem@...emloft.net>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        Rafal Ozieblo <rafalo@...ence.com>,
        Sergio Prado <sergio.prado@...abworks.com>,
        antoine.tenart@...tlin.com,
        Florian Fainelli <f.fainelli@...il.com>, linux@...linux.org.uk,
        Andrew Lunn <andrew@...n.ch>,
        Michal Simek <michal.simek@...inx.com>
Subject: Re: [RFC PATCH 0/3] net: macb: Wake-on-Lan magic packet fixes

Hi Nicolas,

On Mon, Apr 6, 2020 at 7:56 PM Nicolas Ferre
<nicolas.ferre@...rochip.com> wrote:
>
> Hi Harini,
>
> On 03/04/2020 at 15:36, Harini Katakam wrote:
> > Hi Nicolas,
> >
> > On Fri, Apr 3, 2020 at 6:45 PM <nicolas.ferre@...rochip.com> wrote:
> >>
> >> From: Nicolas Ferre <nicolas.ferre@...rochip.com>
<snip>
> >
> > I know that the IP versions from r1p10 have a mechanism to disable DMA queues
> > (bit 0 of the queue pointer register) which is cleaner. But for
> > earlier IP versions,
>
> Which IP name are you referring to? GEM, GEM-GXL? What is the value of
> register 0xFC then?

GEM_GXL

>
> > I remember discussing with Cadence and there is no way to keep RX
> > enabled for WOL
> > with RX DMA disabled. I'm afraid that means there should be a bare
> > minimum memory
> > region with a dummy descriptor if you do not want to process the
> > packets. That memory
> > should also be accessible while the rest of the system is powered
> > down. Please let me
>
> Very interesting information Harini, thanks a lot for having shared it.
>
> My GEM IP has 0xFC at value: 0x00020203. But I don't see a way to keep
> DMA queues disabled by using the famous bit that you mention above.

Yeah, it is not possible in this revision. This is part of the GEM_GXL r1p10 or
higher I think. I can't be sure of all the possible variations of the
revision reg
because the scheme changed at some point but it looks like this:
0x00070100
bits 27:16 (module_ID), bits16:0 (module_revision); they could increase.

Regards,
Harini