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Message-ID: <20200415130034.7zbizr4x4vnxto6a@pengutronix.de>
Date: Wed, 15 Apr 2020 15:00:34 +0200
From: Oleksij Rempel <o.rempel@...gutronix.de>
To: Michal Kubecek <mkubecek@...e.cz>
Cc: netdev@...r.kernel.org, Andrew Lunn <andrew@...n.ch>,
"David S. Miller" <davem@...emloft.net>,
Florian Fainelli <f.fainelli@...il.com>,
Heiner Kallweit <hkallweit1@...il.com>,
Jakub Kicinski <kuba@...nel.org>,
Jonathan Corbet <corbet@....net>,
David Jander <david@...tonic.nl>, kernel@...gutronix.de,
linux-kernel@...r.kernel.org, Russell King <linux@...linux.org.uk>,
mkl@...gutronix.de, Marek Vasut <marex@...x.de>
Subject: Re: [PATCH v1] ethtool: provide UAPI for PHY master/slave
configuration.
On Wed, Apr 15, 2020 at 02:43:43PM +0200, Michal Kubecek wrote:
> On Wed, Apr 15, 2020 at 02:19:40PM +0200, Oleksij Rempel wrote:
> > Cc: Marek Vasut <marex@...x.de>
> >
> > On Wed, Apr 15, 2020 at 02:12:09PM +0200, Oleksij Rempel wrote:
> > > This UAPI is needed for BroadR-Reach 100BASE-T1 devices. Due to lack of
> > > auto-negotiation support, we needed to be able to configure the
> > > MASTER-SLAVE role of the port manually or from an application in user
> > > space.
> > >
> > > The same UAPI can be used for 1000BASE-T or MultiGBASE-T devices to
> > > force MASTER or SLAVE role. See IEEE 802.3-2018:
> > > 22.2.4.3.7 MASTER-SLAVE control register (Register 9)
> > > 22.2.4.3.8 MASTER-SLAVE status register (Register 10)
> > > 40.5.2 MASTER-SLAVE configuration resolution
> > > 45.2.1.185.1 MASTER-SLAVE config value (1.2100.14)
> > > 45.2.7.10 MultiGBASE-T AN control 1 register (Register 7.32)
> > >
> > > The MASTER-SLAVE role affects the clock configuration:
> > >
> > > -------------------------------------------------------------------------------
> > > When the PHY is configured as MASTER, the PMA Transmit function shall
> > > source TX_TCLK from a local clock source. When configured as SLAVE, the
> > > PMA Transmit function shall source TX_TCLK from the clock recovered from
> > > data stream provided by MASTER.
> > >
> > > iMX6Q KSZ9031 XXX
> > > ------\ /-----------\ /------------\
> > > | | | | |
> > > MAC |<----RGMII----->| PHY Slave |<------>| PHY Master |
> > > |<--- 125 MHz ---+-<------/ | | \ |
> > > ------/ \-----------/ \------------/
> > > ^
> > > \-TX_TCLK
> > >
> > > -------------------------------------------------------------------------------
> > >
> > > Since some clock or link related issues are only reproducible in a
> > > specific MASTER-SLAVE-role, MAC and PHY configuration, it is beneficial
> > > to provide generic (not 100BASE-T1 specific) interface to the user space
> > > for configuration flexibility and trouble shooting.
> > >
> > > Signed-off-by: Oleksij Rempel <o.rempel@...gutronix.de>
> > > ---
> [...]
> > > +/* Port mode */
> > > +#define PORT_MODE_MASTER 0x00
> > > +#define PORT_MODE_SLAVE 0x01
> > > +#define PORT_MODE_MASTER_FORCE 0x02
> > > +#define PORT_MODE_SLAVE_FORCE 0x03
> > > +#define PORT_MODE_UNKNOWN 0xff
>
> Shouldn't 0 rather be something like PORT_MODE_UNSUPPORTED or
> PORT_MODE_NONE? If I see correctly, all drivers not setting the new
> field (which would be all drivers right now and almost all later) will
> leave the value at 0 which would be interpreted as PORT_MODE_MASTER.
Yes, you right. I was thinking about it and decided to follow the duplex
code pattern. Will fix in the next version.
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