netdev - Re: [PATCH v2 1/2] net: stmmac: fix enabling socfpga's ptp_ref

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Date:   Sat, 18 Apr 2020 15:02:43 -0700 (PDT)
From:   David Miller <davem@...emloft.net>
To:     julien.beraud@...lia.com
Cc:     peppe.cavallaro@...com, alexandre.torgue@...com,
        joabreu@...opsys.com, netdev@...r.kernel.org
Subject: Re: [PATCH v2 1/2] net: stmmac: fix enabling socfpga's
 ptp_ref_clock

From: Julien Beraud <julien.beraud@...lia.com>
Date: Wed, 15 Apr 2020 14:24:31 +0200

> There are 2 registers to write to enable a ptp ref clock coming from the
> fpga.
> One that enables the usage of the clock from the fpga for emac0 and emac1
> as a ptp ref clock, and the other to allow signals from the fpga to reach
> emac0 and emac1.
> Currently, if the dwmac-socfpga has phymode set to PHY_INTERFACE_MODE_MII,
> PHY_INTERFACE_MODE_GMII, or PHY_INTERFACE_MODE_SGMII, both registers will
> be written and the ptp ref clock will be set as coming from the fpga.
> Separate the 2 register writes to only enable signals from the fpga to
> reach emac0 or emac1 when ptp ref clock is not coming from the fpga.
> 
> Signed-off-by: Julien Beraud <julien.beraud@...lia.com>

Applied.