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Message-Id: <20200418.150253.423349293606830966.davem@davemloft.net>
Date:   Sat, 18 Apr 2020 15:02:53 -0700 (PDT)
From:   David Miller <davem@...emloft.net>
To:     julien.beraud@...lia.com
Cc:     peppe.cavallaro@...com, alexandre.torgue@...com,
        joabreu@...opsys.com, netdev@...r.kernel.org
Subject: Re: [PATCH v2 2/2] net: stmmac: Fix sub-second increment

From: Julien Beraud <julien.beraud@...lia.com>
Date: Wed, 15 Apr 2020 14:24:32 +0200

>     In fine adjustement mode, which is the current default, the sub-second
>     increment register is the number of nanoseconds that will be added to
>     the clock when the accumulator overflows. At each clock cycle, the
>     value of the addend register is added to the accumulator.
>     Currently, we use 20ns = 1e09ns / 50MHz as this value whatever the
>     frequency of the ptp clock actually is.
>     The adjustment is then done on the addend register, only incrementing
>     every X clock cycles X being the ratio between 50MHz and ptp_clock_rate
>     (addend = 2^32 * 50MHz/ptp_clock_rate).
>     This causes the following issues :
>     - In case the frequency of the ptp clock is inferior or equal to 50MHz,
>       the addend value calculation will overflow and the default
>       addend value will be set to 0, causing the clock to not work at
>       all. (For instance, for ptp_clock_rate = 50MHz, addend = 2^32).
>     - The resolution of the timestamping clock is limited to 20ns while it
>       is not needed, thus limiting the accuracy of the timestamping to
>       20ns.
> 
>     Fix this by setting sub-second increment to 2e09ns / ptp_clock_rate.
>     It will allow to reach the minimum possible frequency for
>     ptp_clk_ref, which is 5MHz for GMII 1000Mps Full-Duplex by setting the
>     sub-second-increment to a higher value. For instance, for 25MHz, it
>     gives ssinc = 80ns and default_addend = 2^31.
>     It will also allow to use a lower value for sub-second-increment, thus
>     improving the timestamping accuracy with frequencies higher than
>     100MHz, for instance, for 200MHz, ssinc = 10ns and default_addend =
>     2^31.
> 
> v1->v2:
>  - Remove modifications to the calculation of default addend, which broke
>  compatibility with clock frequencies for which 2000000000 / ptp_clk_freq
>  is not an integer.
>  - Modify description according to discussions.
> 
> Signed-off-by: Julien Beraud <julien.beraud@...lia.com>

Applied.

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