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Message-ID: <82e82079-44fe-8de2-5aa4-65755b21a9cb@intel.com>
Date: Tue, 19 May 2020 12:45:12 -0700
From: Jacob Keller <jacob.e.keller@...el.com>
To: Parav Pandit <parav@...lanox.com>, Jiri Pirko <jiri@...nulli.us>
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Subject: Re: [RFC v2] current devlink extension plan for NICs
On 5/18/2020 10:17 PM, Parav Pandit wrote:
> Hi Jake,
>
>> Ok. So in the smart NIC CPU, we'd see the primary PF and some child PFs,
>> and in the host system we'd see a "primary PF" that is the other end of the
>> associated Child PF, and might be able to manage its own subswitch.
>>
>> Ok this is making more sense now.
>>
>> I think I had imagined that was what subfuntions were. But really
>> subfunctions are a bit different, they're more similar to expanded VFs?
>>
>
> 1. Sub functions are more light weight than VFs because,
> 2. They share the same PCI device (BAR, IRQs) as that of PF/VF on which it is deployed.
> 3. Unlike VFs which are enabled/disabled in bulk, subfunctions are created, deployed in unit of 1.
>
> Since this RFC content is overwhelming, I expanded the SF plumbing details more in [1] in previous RFC version.
> You can replace 'devlink slice' with 'devlink port func' in [1].
>
> [1] https://marc.info/?l=linux-netdev&m=158555928517777&w=2
>
Thanks! Indeed, this makes things a lot more clear to me now.
Regards,
Jake
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