netdev - Re: [net-next,PATCH 4/4] dt-bindings: mdio-ipq4019: add clock support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Fri, 3 Jul 2020 09:44:43 +0200
From:   Robert Marko <robert.marko@...tura.hr>
To:     Florian Fainelli <f.fainelli@...il.com>
Cc:     Andrew Lunn <andrew@...n.ch>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Russell King - ARM Linux admin <linux@...linux.org.uk>,
        David Miller <davem@...emloft.net>, kuba@...nel.org,
        netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        robh+dt@...nel.org
Subject: Re: [net-next,PATCH 4/4] dt-bindings: mdio-ipq4019: add clock support

On Thu, Jul 2, 2020 at 10:04 PM Florian Fainelli <f.fainelli@...il.com> wrote:
>
>
>
> On 7/2/2020 12:18 PM, Robert Marko wrote:
> > On Thu, Jul 2, 2020 at 3:38 PM Andrew Lunn <andrew@...n.ch> wrote:
> >>
> >>> +  clock-frequency:
> >>> +    default: 100000000
> >>
> >> IEEE 802.3 says the default should be 2.5MHz. Some PHYs will go
> >> faster, but 100MHz seems unlikely!
> > This MDIO controller has an internal divider, by default its set for
> > 100MHz clock.
> > In IPQ4019 MDIO clock is not controllable but in IPQ6018 etc it's controllable.
> > That is the only combination I have currently seen used by Qualcomm.
>
> Not sure I understand here, the 'clock-frequency' is supposed to denote
> the MDIO bus output clock frequency, that is the frequency at which all
> MDIO devices are going to operate at. Is this 100MHz a clock that feeds
> into the MDIO block and get internally divided by a programmable
> register to obtain an output MDIO clock?
Yes, in this case that 100MHz comes from the GCC clock controller and
is then internally divided by the MDIO.
I do not know what is the actual output MDIO bus frequency as
datasheet only denotes that MDC divide
bits in the mode register are set for 100MHz incoming clock.
> --
> Florian