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Message-Id: <20200704124507.3336497-2-olteanv@gmail.com>
Date: Sat, 4 Jul 2020 15:45:02 +0300
From: Vladimir Oltean <olteanv@...il.com>
To: davem@...emloft.net, netdev@...r.kernel.org
Cc: andrew@...n.ch, f.fainelli@...il.com, vivien.didelot@...il.com,
claudiu.manoil@....com, alexandru.marginean@....com,
ioana.ciornei@....com, linux@...linux.org.uk
Subject: [PATCH v2 net-next 1/6] net: dsa: felix: clarify the intention of writes to MII_BMCR
From: Vladimir Oltean <vladimir.oltean@....com>
The driver appears to write to BMCR_SPEED and BMCR_DUPLEX, fields which
are read-only, since they are actually configured through the
vendor-specific IF_MODE (0x14) register.
But the reason we're writing back the read-only values of MII_BMCR is to
alter these writable fields:
BMCR_RESET
BMCR_LOOPBACK
BMCR_ANENABLE
BMCR_PDOWN
BMCR_ISOLATE
BMCR_ANRESTART
In particular, the only field which is really relevant to this driver is
BMCR_ANENABLE. Clarify that intention by spelling it out, using
phy_set_bits and phy_clear_bits.
The driver also made a few writes to BMCR_RESET and BMCR_ANRESTART which
are unnecessary and may temporarily disrupt the link to the PHY. Remove
them.
Signed-off-by: Vladimir Oltean <vladimir.oltean@....com>
---
Changes in v2:
Patch is new.
drivers/net/dsa/ocelot/felix_vsc9959.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c
index 2067776773f7..9f4c8343652f 100644
--- a/drivers/net/dsa/ocelot/felix_vsc9959.c
+++ b/drivers/net/dsa/ocelot/felix_vsc9959.c
@@ -815,7 +815,7 @@ static void vsc9959_pcs_init_sgmii(struct phy_device *pcs,
phy_write(pcs, ENETC_PCS_LINK_TIMER2,
ENETC_PCS_LINK_TIMER2_VAL);
- phy_write(pcs, MII_BMCR, BMCR_ANRESTART | BMCR_ANENABLE);
+ phy_set_bits(pcs, MII_BMCR, BMCR_ANENABLE);
} else {
int speed;
@@ -845,10 +845,7 @@ static void vsc9959_pcs_init_sgmii(struct phy_device *pcs,
ENETC_PCS_IF_MODE_SGMII_EN |
ENETC_PCS_IF_MODE_SGMII_SPEED(speed));
- /* Yes, not a mistake: speed is given by IF_MODE. */
- phy_write(pcs, MII_BMCR, BMCR_RESET |
- BMCR_SPEED1000 |
- BMCR_FULLDPLX);
+ phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE);
}
}
@@ -882,9 +879,7 @@ static void vsc9959_pcs_init_2500basex(struct phy_device *pcs,
ENETC_PCS_IF_MODE_SGMII_EN |
ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_2500));
- phy_write(pcs, MII_BMCR, BMCR_SPEED1000 |
- BMCR_FULLDPLX |
- BMCR_RESET);
+ phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE);
}
static void vsc9959_pcs_init_usxgmii(struct phy_device *pcs,
--
2.25.1
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