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Date:   Mon, 13 Jul 2020 13:40:57 -0700
From:   Eric Dumazet <eric.dumazet@...il.com>
To:     Shay Agroskin <shayagr@...zon.com>,
        Eric Dumazet <eric.dumazet@...il.com>
Cc:     akiyano@...zon.com, davem@...emloft.net, netdev@...r.kernel.org,
        dwmw@...zon.com, zorik@...zon.com, matua@...zon.com,
        saeedb@...zon.com, msw@...zon.com, aliguori@...zon.com,
        nafea@...zon.com, gtzalik@...zon.com, netanel@...zon.com,
        alisaidi@...zon.com, benh@...zon.com, ndagan@...zon.com,
        sameehj@...zon.com
Subject: Re: [PATCH V2 net-next 1/7] net: ena: avoid unnecessary rearming of
 interrupt vector when busy-polling



On 7/13/20 12:39 PM, Shay Agroskin wrote:
> 
> Eric Dumazet <eric.dumazet@...il.com> writes:
> 

>>> +     WRITE_ONCE(ena_napi->interrupts_masked, true);
>>> +     smp_wmb(); /* write interrupts_masked before calling napi */
>>
>> It is not clear where is the paired smp_wmb()
>>
> Can you please explain what you mean ? The idea of adding the store barrier here is to ensure that the WRITE_ONCE(…) invocation is executed before
> invoking the napi soft irq. From what I gathered using this command would result in compiler barrier (which would prevent it from executing the bool store after napi scheduling) on x86
> and a memory barrier on ARM64 machines which have a weaker consistency model.

Every time you add a smp_wmb() somewhere, the question is raised where the opposite barrier (usually smp_rmb())
is used.

You should document this, pointing where is the opposite smp_rmb()

If you can not find it (READ_ONCE() has no implied smp_rmb()), then
something might be wrong in your patch.

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