lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Mon, 13 Jul 2020 15:03:23 -0700
From:   Jakub Kicinski <kuba@...nel.org>
To:     Igor Russkikh <irusskikh@...vell.com>
Cc:     <netdev@...r.kernel.org>, "David S . Miller" <davem@...emloft.net>,
        Mark Starovoytov <mstarovoitov@...vell.com>,
        Dmitry Bogdanov <dbogdanov@...vell.com>
Subject: Re: [PATCH net-next 03/10] net: atlantic: additional per-queue
 stats

On Mon, 13 Jul 2020 14:42:26 +0300 Igor Russkikh wrote:
> From: Dmitry Bogdanov <dbogdanov@...vell.com>
> 
> This patch adds additional per-queue stats, these could
> be useful for debugging and diagnostics.
> 
> Signed-off-by: Dmitry Bogdanov <dbogdanov@...vell.com>
> Signed-off-by: Mark Starovoytov <mstarovoitov@...vell.com>
> Signed-off-by: Igor Russkikh <irusskikh@...vell.com>

> diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ring.h b/drivers/net/ethernet/aquantia/atlantic/aq_ring.h
> index 2c96f20f6289..c31d4642d280 100644
> --- a/drivers/net/ethernet/aquantia/atlantic/aq_ring.h
> +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ring.h
> @@ -1,7 +1,8 @@
>  /* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * aQuantia Corporation Network Driver
> - * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved
> +/* Atlantic Network Driver
> + *
> + * Copyright (C) 2014-2019 aQuantia Corporation
> + * Copyright (C) 2019-2020 Marvell International Ltd.
>   */
>  
>  /* File aq_ring.h: Declaration of functions for Rx/Tx rings. */
> @@ -93,6 +94,10 @@ struct aq_ring_stats_rx_s {
>  	u64 bytes;
>  	u64 lro_packets;
>  	u64 jumbo_packets;
> +	u64 alloc_fails;
> +	u64 skb_alloc_fails;
> +	u64 polls;
> +	u64 irqs;
>  	u64 pg_losts;
>  	u64 pg_flips;
>  	u64 pg_reuses;

> @@ -44,6 +45,7 @@ static int aq_vec_poll(struct napi_struct *napi, int budget)
>  	} else {
>  		for (i = 0U, ring = self->ring[0];
>  			self->tx_rings > i; ++i, ring = self->ring[i]) {
> +			ring[AQ_VEC_RX_ID].stats.rx.polls++;

You need to use the u64_stats_update_* infrastructure or make these
stats smaller than u64, cause on non-64bit machines where the stats
will be updated 32bit-by-32bit meaning readers can see a half-updated
counter..

>  			if (self->aq_hw_ops->hw_ring_tx_head_update) {
>  				err = self->aq_hw_ops->hw_ring_tx_head_update(
>  							self->aq_hw,
> @@ -314,6 +316,7 @@ irqreturn_t aq_vec_isr(int irq, void *private)
>  		err = -EINVAL;
>  		goto err_exit;
>  	}
> +	self->ring[0][AQ_VEC_RX_ID].stats.rx.irqs++;

Why do you need this? Every IRQ has a firing counter in
/proc/interrupts.

>  	napi_schedule(&self->napi);
>  
>  err_exit:

Powered by blists - more mailing lists