netdev - Re: [PATCH V3 net-next 1/8] net: ena: avoid unnecessary rearming of interrupt vector when busy-polling

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Date:   Thu, 16 Jul 2020 17:52:39 -0700
From:   Jakub Kicinski <kuba@...nel.org>
To:     <akiyano@...zon.com>
Cc:     <davem@...emloft.net>, <netdev@...r.kernel.org>, <dwmw@...zon.com>,
        <zorik@...zon.com>, <matua@...zon.com>, <saeedb@...zon.com>,
        <msw@...zon.com>, <aliguori@...zon.com>, <nafea@...zon.com>,
        <gtzalik@...zon.com>, <netanel@...zon.com>, <alisaidi@...zon.com>,
        <benh@...zon.com>, <ndagan@...zon.com>, <shayagr@...zon.com>,
        <sameehj@...zon.com>, Eric Dumazet <eric.dumazet@...il.com>
Subject: Re: [PATCH V3 net-next 1/8] net: ena: avoid unnecessary rearming of
 interrupt vector when busy-polling

On Thu, 16 Jul 2020 21:10:03 +0300 akiyano@...zon.com wrote:
> This patch doesn't require smp_rmb() instruction in the napi routine
> because it assumes cache coherency between two cores. I.e. the
> 'interrupts_masked' flag set would be seen by the napi routine, even if
> the flag is stored in L1 cache.
> To the best of my knowledge this assumption holds for ARM64 and x86_64
> architecture which use a MESI like cache coherency model.

If that's the case - for those architectures smb_rmb() should be defined
to barrier(). Why can't you adhere to kernel's memory model, rather
than guessing the architecture in the driver.